total.tan.rpt

数字显示当前的小时、分钟、秒； 2、可以预置为12小时计时显示和24小时计时显示； 3、一个调节键

Timing Analyzer report for TOTAL
Thu Oct 30 11:11:40 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK_1KHZ'
  6. Clock Setup: 'SET_TIME[1]'
  7. Clock Setup: 'SET_TIME[0]'
  8. Clock Setup: 'CLOCK_MAICHONG'
  9. Clock Hold: 'SET_TIME[1]'
 10. Clock Hold: 'SET_TIME[0]'
 11. Clock Hold: 'CLOCK_MAICHONG'
 12. tsu
 13. tco
 14. tpd
 15. th
 16. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                ;
+-------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+-------------------+----------------+----------------+--------------+
; Type                          ; Slack                                    ; Required Time ; Actual Time                      ; From                ; To                ; From Clock     ; To Clock       ; Failed Paths ;
+-------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+-------------------+----------------+----------------+--------------+
; Worst-case tsu                ; N/A                                      ; None          ; 1.261 ns                         ; MODEL_INPUT         ; HOUR:inst3|CQI[5] ;                ; CLOCK_MAICHONG ; 0            ;
; Worst-case tco                ; N/A                                      ; None          ; 35.308 ns                        ; HOUR:inst3|CQI[1]   ; DAOUT[1]          ; CLK_1KHZ       ;                ; 0            ;
; Worst-case tpd                ; N/A                                      ; None          ; 7.643 ns                         ; CLK_2KHZ            ; ALERT_OUTPUT      ;                ;                ; 0            ;
; Worst-case th                 ; N/A                                      ; None          ; 22.597 ns                        ; RESET               ; MINUTE:inst|COUT  ;                ; CLK_1KHZ       ; 0            ;
; Clock Setup: 'SET_TIME[0]'    ; N/A                                      ; None          ; 88.30 MHz ( period = 11.325 ns ) ; HOUR:inst3|CQI[2]   ; HOUR:inst3|CQI[7] ; SET_TIME[0]    ; SET_TIME[0]    ; 0            ;
; Clock Setup: 'SET_TIME[1]'    ; N/A                                      ; None          ; 88.88 MHz ( period = 11.251 ns ) ; HOUR:inst3|CQI[2]   ; HOUR:inst3|CQI[7] ; SET_TIME[1]    ; SET_TIME[1]    ; 0            ;
; Clock Setup: 'CLOCK_MAICHONG' ; N/A                                      ; None          ; 88.90 MHz ( period = 11.249 ns ) ; HOUR:inst3|CQI[2]   ; HOUR:inst3|CQI[7] ; CLOCK_MAICHONG ; CLOCK_MAICHONG ; 0            ;
; Clock Setup: 'CLK_1KHZ'       ; N/A                                      ; None          ; 105.74 MHz ( period = 9.457 ns ) ; MINUTE:inst|CNT0[0] ; ALERT:inst6|QLK   ; CLK_1KHZ       ; CLK_1KHZ       ; 0            ;
; Clock Hold: 'SET_TIME[0]'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; HOUR:inst3|CQI[4]   ; HOUR:inst3|CQI[4] ; SET_TIME[0]    ; SET_TIME[0]    ; 115          ;
; Clock Hold: 'SET_TIME[1]'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; HOUR:inst3|CQI[4]   ; HOUR:inst3|CQI[4] ; SET_TIME[1]    ; SET_TIME[1]    ; 115          ;
; Clock Hold: 'CLOCK_MAICHONG'  ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; HOUR:inst3|CQI[4]   ; HOUR:inst3|CQI[4] ; CLOCK_MAICHONG ; CLOCK_MAICHONG ; 115          ;
; Total number of failed paths  ;                                          ;               ;                                  ;                     ;                   ;                ;                ; 345          ;
+-------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+-------------------+----------------+----------------+--------------+