chenxu.txt

&#61548 系统设置一个两位BCD码倒计时计数器（计数脉冲1HZ）

我的程序:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY traffic IS
  PORT(clk,s:IN STD_LOGIC;
D3,D2,D1,D0,G3,G2,G1,G0:OUT STD_LOGIC;
MR,MY,MG,CR,CY,CG:OUT STD_LOGIC);
END ENTITY traffic;
ARCHITECTURE arch OF traffic IS
  TYPE STATES IS(s3,s2,s1,s0);
  SIGNAL state:states:=s0;
  SIGNAL next_state:states:=s0;
  SIGNAL count0:STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL count1:STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL data0:STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL data1:STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL MC:STD_LOGIC_VECTOR(5 DOWNTO 0);
  SIGNAL cao,en,load:STD_LOGIC;
BEGIN
P1:ROCESS(clk,en,load)
     BEGIN
    IF RISING_EDGE(clk)THEN
        IF en='1' THEN
            IF load='1'THEN
               count0<=data0;
                ELSIF count0="0000"THEN
                count0<="1001";
                ELSE count0<=count0-'1';
                END IF;
             END IF;
        END IF;
END PROCESS P1;
P2:ROCESS(clk)
  BEGIN
   IF clk='0' THEN
     IF count0="0000"THEN
       cao<='1';
       ELSE cao<='0';
     END IF;
   END IF;
END PROCESS P2;
P3:ROCESS(clk,load)
   BEGIN
    IF (RISING_EDGE(clk) AND cao='1') THEN
     IF load='1' THEN
       count1<=data1;
         ELSIF count1<="0000"THEN
           count1<="1001";
         ELSE count1<=count1-'1';
         END IF;
     END IF;
END PROCESS P3;
P4:ROCESS(state,clk,s,count0,count1,en)
BEGIN
IF en='1' THEN
CASE state IS
   WHEN s0=>MC<="001100";
     IF FALLING_EDGE(clk)THEN
       IF(count0="0000" AND count1="0000")THEN
         IF s='0'THEN
           en<='0';
         ELSE
           en<='1';
           load<='1';
           data0<="0100";
           data1<="0000";
           next_state<=s1;
           state<=next_state;
         END IF;
       ELSE load<='0';
       END IF;
     END IF;
   WHEN s1=>MC<="010100";
    IF FALLING_EDGE(clk)THEN
      IF(count0="0000" AND count1="0000")THEN
         load<='1';
         data0<="0000";
         data1<="0010";
         next_state<=s2;
         state<=next_state;
        ELSE load<='0';
        END IF;
    END IF;
  WHEN s2=>MC<="100001";
    IF FALLING_EDGE(clk)THEN
       IF s='1' THEN
          IF(count0="0000" AND count1="0000")THEN 
           load<='1';
           data0<="0100";
           data1<="0000";
           next_state<=s3;
           state<=next_state;
          ELSE load<='0';
          END IF;
       ELSE load<='1';
           data0<="0100";
           data1<="0000";
           next_state<=s3;
           state<=next_state;
       END IF;
     END IF;
   WHEN s3=>MC<="100010";
   IF FALLING_EDGE(clk)THEN
    IF(count0="0000" AND count1="0000"THEN
        load<='1';
        data0<="0000";
        data1<="0110";
        next_state<=s0;
        state<=next_state;
    ELSE load<='0';
    END IF;
   END IF;
END CASE;
END IF;
END PROCESS P4;
D3<=count1(3);D2<=count1(2);D1<=count1(1);D0<=count1(0);
G3<=count0(3);G2<=count0(2);G1<=count0(1);G0<=count0(0);
MR<=MC(5);MY<=MC(4);MG<=MC(3);
CR<=MC(2);CY<=MC(1);CG<=MC(0);
END ARCHITECTURE arch;



报错:signal paramenter in a subprogram is not supported