📄 debounce.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register \\sampling_signal:q\[4\] \\cleared_push:push 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"\\sampling_signal:q\[4\]\" and destination register \"\\cleared_push:push\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.315 ns + Longest register register " "Info: + Longest register to register delay is 1.315 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\sampling_signal:q\[4\] 1 REG LCFF_X39_Y21_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y21_N7; Fanout = 3; REG Node = '\\sampling_signal:q\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { \sampling_signal:q[4] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.053 ns) 0.355 ns sample 2 COMB LCCOMB_X39_Y21_N18 3 " "Info: 2: + IC(0.302 ns) + CELL(0.053 ns) = 0.355 ns; Loc. = LCCOMB_X39_Y21_N18; Fanout = 3; COMB Node = 'sample'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.355 ns" { \sampling_signal:q[4] sample } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.214 ns) + CELL(0.746 ns) 1.315 ns \\cleared_push:push 3 REG LCFF_X39_Y21_N17 1 " "Info: 3: + IC(0.214 ns) + CELL(0.746 ns) = 1.315 ns; Loc. = LCFF_X39_Y21_N17; Fanout = 1; REG Node = '\\cleared_push:push'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.960 ns" { sample \cleared_push:push } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.799 ns ( 60.76 % ) " "Info: Total cell delay = 0.799 ns ( 60.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.516 ns ( 39.24 % ) " "Info: Total interconnect delay = 0.516 ns ( 39.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.315 ns" { \sampling_signal:q[4] sample \cleared_push:push } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.315 ns" { \sampling_signal:q[4] {} sample {} \cleared_push:push {} } { 0.000ns 0.302ns 0.214ns } { 0.000ns 0.053ns 0.746ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.490 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns \\cleared_push:push 3 REG LCFF_X39_Y21_N17 1 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N17; Fanout = 1; REG Node = '\\cleared_push:push'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk~clkctrl \cleared_push:push } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:push } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:push {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.490 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns \\sampling_signal:q\[4\] 3 REG LCFF_X39_Y21_N7 3 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N7; Fanout = 3; REG Node = '\\sampling_signal:q\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk~clkctrl \sampling_signal:q[4] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \sampling_signal:q[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \sampling_signal:q[4] {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:push } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:push {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \sampling_signal:q[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \sampling_signal:q[4] {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.315 ns" { \sampling_signal:q[4] sample \cleared_push:push } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.315 ns" { \sampling_signal:q[4] {} sample {} \cleared_push:push {} } { 0.000ns 0.302ns 0.214ns } { 0.000ns 0.053ns 0.746ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:push } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:push {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \sampling_signal:q[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \sampling_signal:q[4] {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { \cleared_push:push } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { \cleared_push:push {} } { } { } "" } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "\\cleared_push:dff0 touch clk 2.052 ns register " "Info: tsu for register \"\\cleared_push:dff0\" (data pin = \"touch\", clock pin = \"clk\") is 2.052 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.452 ns + Longest pin register " "Info: + Longest pin to register delay is 4.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 0.800 ns touch 1 PIN PIN_H6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_H6; Fanout = 1; PIN Node = 'touch'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { touch } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.444 ns) + CELL(0.053 ns) 4.297 ns \\cleared_push:dff0~feeder 2 COMB LCCOMB_X39_Y21_N30 1 " "Info: 2: + IC(3.444 ns) + CELL(0.053 ns) = 4.297 ns; Loc. = LCCOMB_X39_Y21_N30; Fanout = 1; COMB Node = '\\cleared_push:dff0~feeder'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.497 ns" { touch \cleared_push:dff0~feeder } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.452 ns \\cleared_push:dff0 3 REG LCFF_X39_Y21_N31 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.452 ns; Loc. = LCFF_X39_Y21_N31; Fanout = 2; REG Node = '\\cleared_push:dff0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { \cleared_push:dff0~feeder \cleared_push:dff0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.008 ns ( 22.64 % ) " "Info: Total cell delay = 1.008 ns ( 22.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.444 ns ( 77.36 % ) " "Info: Total interconnect delay = 3.444 ns ( 77.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.452 ns" { touch \cleared_push:dff0~feeder \cleared_push:dff0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.452 ns" { touch {} touch~combout {} \cleared_push:dff0~feeder {} \cleared_push:dff0 {} } { 0.000ns 0.000ns 3.444ns 0.000ns } { 0.000ns 0.800ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.490 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns \\cleared_push:dff0 3 REG LCFF_X39_Y21_N31 2 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N31; Fanout = 2; REG Node = '\\cleared_push:dff0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk~clkctrl \cleared_push:dff0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:dff0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:dff0 {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.452 ns" { touch \cleared_push:dff0~feeder \cleared_push:dff0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.452 ns" { touch {} touch~combout {} \cleared_push:dff0~feeder {} \cleared_push:dff0 {} } { 0.000ns 0.000ns 3.444ns 0.000ns } { 0.000ns 0.800ns 0.053ns 0.155ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:dff0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:dff0 {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk push_out \\cleared_push:q1 5.585 ns register " "Info: tco from clock \"clk\" to destination pin \"push_out\" through register \"\\cleared_push:q1\" is 5.585 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.490 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns \\cleared_push:q1 3 REG LCFF_X39_Y21_N9 2 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N9; Fanout = 2; REG Node = '\\cleared_push:q1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk~clkctrl \cleared_push:q1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:q1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:q1 {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.001 ns + Longest register pin " "Info: + Longest register to pin delay is 3.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\cleared_push:q1 1 REG LCFF_X39_Y21_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y21_N9; Fanout = 2; REG Node = '\\cleared_push:q1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { \cleared_push:q1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.272 ns) 0.525 ns push_out~0 2 COMB LCCOMB_X39_Y21_N20 1 " "Info: 2: + IC(0.253 ns) + CELL(0.272 ns) = 0.525 ns; Loc. = LCCOMB_X39_Y21_N20; Fanout = 1; COMB Node = 'push_out~0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.525 ns" { \cleared_push:q1 push_out~0 } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(2.154 ns) 3.001 ns push_out 3 PIN PIN_G1 0 " "Info: 3: + IC(0.322 ns) + CELL(2.154 ns) = 3.001 ns; Loc. = PIN_G1; Fanout = 0; PIN Node = 'push_out'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.476 ns" { push_out~0 push_out } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.426 ns ( 80.84 % ) " "Info: Total cell delay = 2.426 ns ( 80.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.575 ns ( 19.16 % ) " "Info: Total interconnect delay = 0.575 ns ( 19.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.001 ns" { \cleared_push:q1 push_out~0 push_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.001 ns" { \cleared_push:q1 {} push_out~0 {} push_out {} } { 0.000ns 0.253ns 0.322ns } { 0.000ns 0.272ns 2.154ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:q1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:q1 {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.001 ns" { \cleared_push:q1 push_out~0 push_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.001 ns" { \cleared_push:q1 {} push_out~0 {} push_out {} } { 0.000ns 0.253ns 0.322ns } { 0.000ns 0.272ns 2.154ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "\\cleared_push:dff0 touch clk -1.813 ns register " "Info: th for register \"\\cleared_push:dff0\" (data pin = \"touch\", clock pin = \"clk\") is -1.813 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.490 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns \\cleared_push:dff0 3 REG LCFF_X39_Y21_N31 2 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N31; Fanout = 2; REG Node = '\\cleared_push:dff0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk~clkctrl \cleared_push:dff0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:dff0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:dff0 {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" { } { } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.452 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 0.800 ns touch 1 PIN PIN_H6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_H6; Fanout = 1; PIN Node = 'touch'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { touch } "NODE_NAME" } } { "debounce.vhd" "" { Text "D:/CPLD/bitch/debounce.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.444 ns) + CELL(0.053 ns) 4.297 ns \\cleared_push:dff0~feeder 2 COMB LCCOMB_X39_Y21_N30 1 " "Info: 2: + IC(3.444 ns) + CELL(0.053 ns) = 4.297 ns; Loc. = LCCOMB_X39_Y21_N30; Fanout = 1; COMB Node = '\\cleared_push:dff0~feeder'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.497 ns" { touch \cleared_push:dff0~feeder } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.452 ns \\cleared_push:dff0 3 REG LCFF_X39_Y21_N31 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.452 ns; Loc. = LCFF_X39_Y21_N31; Fanout = 2; REG Node = '\\cleared_push:dff0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { \cleared_push:dff0~feeder \cleared_push:dff0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.008 ns ( 22.64 % ) " "Info: Total cell delay = 1.008 ns ( 22.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.444 ns ( 77.36 % ) " "Info: Total interconnect delay = 3.444 ns ( 77.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.452 ns" { touch \cleared_push:dff0~feeder \cleared_push:dff0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.452 ns" { touch {} touch~combout {} \cleared_push:dff0~feeder {} \cleared_push:dff0 {} } { 0.000ns 0.000ns 3.444ns 0.000ns } { 0.000ns 0.800ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl \cleared_push:dff0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} \cleared_push:dff0 {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.452 ns" { touch \cleared_push:dff0~feeder \cleared_push:dff0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.452 ns" { touch {} touch~combout {} \cleared_push:dff0~feeder {} \cleared_push:dff0 {} } { 0.000ns 0.000ns 3.444ns 0.000ns } { 0.000ns 0.800ns 0.053ns 0.155ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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