debounce.vhd.bak

基于VHDL的键盘去抖动电路 基于VHDL的键盘去抖动电路

--content definition of component "debounce" 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
--io signal declaraction 
entity debounce is 
  port(clk: in std_logic; --basic clock input   
    clr:in std_logic; 
    touch: in std_logic; --push button signal   
      push_out: out std_logic); --cleared push botton signal 
end debounce; 
architecture arch of debounce is   
  signal sample: std_logic; 
--declaraction of self_built sampling pulse from clock 
begin 
 sampling_signal: block 
--input clk 
--output sample 
  signal delay:std_logic; --one_step delay 
  signal q: std_logic_vector(4 downto 0); --osc/2^5=32hz(31.25ms) 
 begin 
   process(clk) 
   begin  
   if clr='1' then  
    q<="00000"; 
    delay<='0'; 
   elsif rising_edge(clk) then 
    delay<=q(4);  
    q<=q+1; 
   end if;  
      sample<=q(4) and not delay; --leading_edge differentiating 
   end process; 
 end block sampling_signal; 
--cleared push botton signal generation 
cleared_push:block 
--input:clk,sample,touch 
--output:push_out 
signal dff0,dff1:std_logic; --two_step delay ff 
signal push:std_logic; --output of rsff for push signal 
signal q1,q2:std_logic; 
begin 
 process(clk) 
 begin  
    if clr='1' then 
   dff0<='0'; 
   dff1<='0'; 
   push<='0'; 
    elsif rising_edge(clk) then 
   if sample='1' then  
    dff1<=dff0; 
    dff0<=touch; 
    push<=dff0 and dff1; 
   end if; 
   end if; 
 end process; 
 process(clk) 
 begin 
    if clr='1' then 
   q2<='0'; 
   q1<='0'; 
    elsif rising_edge(clk) then 
   q2<=q1; 
   q1<=push; 
 end if; 
    push_out<=q1 and not q2; 
 end process; 
 end block cleared_push; 
end arch;