debounce.tan.rpt

基于VHDL的键盘去抖动电路 基于VHDL的键盘去抖动电路

; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; \cleared_push:push     ; \cleared_push:q1       ; clk        ; clk      ; None                        ; None                      ; 0.511 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; \cleared_push:dff0     ; \cleared_push:push     ; clk        ; clk      ; None                        ; None                      ; 0.417 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; \cleared_push:dff0     ; \cleared_push:dff1     ; clk        ; clk      ; None                        ; None                      ; 0.415 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; \sampling_signal:q[0]  ; \sampling_signal:q[0]  ; clk        ; clk      ; None                        ; None                      ; 0.396 ns                ;
+-------+------------------------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------+
; tsu                                                                       ;
+-------+--------------+------------+-------+--------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To                 ; To Clock ;
+-------+--------------+------------+-------+--------------------+----------+
; N/A   ; None         ; 2.052 ns   ; touch ; \cleared_push:dff0 ; clk      ;
+-------+--------------+------------+-------+--------------------+----------+


+------------------------------------------------------------------------------+
; tco                                                                          ;
+-------+--------------+------------+------------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From             ; To       ; From Clock ;
+-------+--------------+------------+------------------+----------+------------+
; N/A   ; None         ; 5.585 ns   ; \cleared_push:q1 ; push_out ; clk        ;
; N/A   ; None         ; 5.301 ns   ; \cleared_push:q2 ; push_out ; clk        ;
+-------+--------------+------------+------------------+----------+------------+


+---------------------------------------------------------------------------------+
; th                                                                              ;
+---------------+-------------+-----------+-------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                 ; To Clock ;
+---------------+-------------+-----------+-------+--------------------+----------+
; N/A           ; None        ; -1.813 ns ; touch ; \cleared_push:dff0 ; clk      ;
+---------------+-------------+-----------+-------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Sat Nov 08 12:27:58 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off debounce -c debounce --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "\sampling_signal:q[4]" and destination register "\cleared_push:push"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.315 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y21_N7; Fanout = 3; REG Node = '\sampling_signal:q[4]'
            Info: 2: + IC(0.302 ns) + CELL(0.053 ns) = 0.355 ns; Loc. = LCCOMB_X39_Y21_N18; Fanout = 3; COMB Node = 'sample'
            Info: 3: + IC(0.214 ns) + CELL(0.746 ns) = 1.315 ns; Loc. = LCFF_X39_Y21_N17; Fanout = 1; REG Node = '\cleared_push:push'
            Info: Total cell delay = 0.799 ns ( 60.76 % )
            Info: Total interconnect delay = 0.516 ns ( 39.24 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.490 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N17; Fanout = 1; REG Node = '\cleared_push:push'
                Info: Total cell delay = 1.472 ns ( 59.12 % )
                Info: Total interconnect delay = 1.018 ns ( 40.88 % )
            Info: - Longest clock path from clock "clk" to source register is 2.490 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N7; Fanout = 3; REG Node = '\sampling_signal:q[4]'
                Info: Total cell delay = 1.472 ns ( 59.12 % )
                Info: Total interconnect delay = 1.018 ns ( 40.88 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "\cleared_push:dff0" (data pin = "touch", clock pin = "clk") is 2.052 ns
    Info: + Longest pin to register delay is 4.452 ns
        Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_H6; Fanout = 1; PIN Node = 'touch'
        Info: 2: + IC(3.444 ns) + CELL(0.053 ns) = 4.297 ns; Loc. = LCCOMB_X39_Y21_N30; Fanout = 1; COMB Node = '\cleared_push:dff0~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.452 ns; Loc. = LCFF_X39_Y21_N31; Fanout = 2; REG Node = '\cleared_push:dff0'
        Info: Total cell delay = 1.008 ns ( 22.64 % )
        Info: Total interconnect delay = 3.444 ns ( 77.36 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.490 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N31; Fanout = 2; REG Node = '\cleared_push:dff0'
        Info: Total cell delay = 1.472 ns ( 59.12 % )
        Info: Total interconnect delay = 1.018 ns ( 40.88 % )
Info: tco from clock "clk" to destination pin "push_out" through register "\cleared_push:q1" is 5.585 ns
    Info: + Longest clock path from clock "clk" to source register is 2.490 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N9; Fanout = 2; REG Node = '\cleared_push:q1'
        Info: Total cell delay = 1.472 ns ( 59.12 % )
        Info: Total interconnect delay = 1.018 ns ( 40.88 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.001 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y21_N9; Fanout = 2; REG Node = '\cleared_push:q1'
        Info: 2: + IC(0.253 ns) + CELL(0.272 ns) = 0.525 ns; Loc. = LCCOMB_X39_Y21_N20; Fanout = 1; COMB Node = 'push_out~0'
        Info: 3: + IC(0.322 ns) + CELL(2.154 ns) = 3.001 ns; Loc. = PIN_G1; Fanout = 0; PIN Node = 'push_out'
        Info: Total cell delay = 2.426 ns ( 80.84 % )
        Info: Total interconnect delay = 0.575 ns ( 19.16 % )
Info: th for register "\cleared_push:dff0" (data pin = "touch", clock pin = "clk") is -1.813 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.490 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X39_Y21_N31; Fanout = 2; REG Node = '\cleared_push:dff0'
        Info: Total cell delay = 1.472 ns ( 59.12 % )
        Info: Total interconnect delay = 1.018 ns ( 40.88 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 4.452 ns
        Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_H6; Fanout = 1; PIN Node = 'touch'
        Info: 2: + IC(3.444 ns) + CELL(0.053 ns) = 4.297 ns; Loc. = LCCOMB_X39_Y21_N30; Fanout = 1; COMB Node = '\cleared_push:dff0~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.452 ns; Loc. = LCFF_X39_Y21_N31; Fanout = 2; REG Node = '\cleared_push:dff0'
        Info: Total cell delay = 1.008 ns ( 22.64 % )
        Info: Total interconnect delay = 3.444 ns ( 77.36 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 118 megabytes of memory during processing
    Info: Processing ended: Sat Nov 08 12:27:59 2008
    Info: Elapsed time: 00:00:01