lcd_init0504.v

液晶显示驱动源程序代码

module lcd_283rb06(cs,sclk,sdi,reset,clock);
output cs;
output sclk;
output sdi;
input reset;
input clock;  //25MHz (39.6ns)

reg [15:0] command[0:52];
reg [15:0] data[0:52];
reg [15:0] data_tmp;

reg [9:0]number;
reg [7:0]index;
reg sclk;
reg sclk2;
reg clock2;
reg sdi;
reg cs;
reg [7:0]state;
//reg [5:0]count;
reg flag_command;
reg start;
reg [7:0]cs_num;

reg flag_20ms;
reg flag_10ms;
reg flag_200ms;
reg flag_50ms;
reg clk_cnt;
reg clk_cnt_20;
reg clk_cnt_10;
reg clk_cnt_200;
reg clk_cnt_50;
reg clk_cnt2;
reg [5:0]init_num;
reg flag_inverse;

parameter present_cnt=10'd2,//present_cnt=10'd10000
		ready=8'd0,
		bit1=8'd1,
		bit2=8'd2,
		bit3=8'd3,
		bit4=8'd3,
		bit5=8'd4,
		bit6=8'd5,
		bit7=8'd7,
		bit8=8'd8,
		bit9=8'd9,
		bit10=8'd10,
		bit11=8'd11,
		bit12=8'd12,
		bit13=8'd13,
		bit14=8'd14,
		bit15=8'd15,
		bit16=8'd16,
		bit17=8'd17,
		bit18=8'd18,
		bit19=8'd19,
		bit20=8'd20,
		bit21=8'd21,
		bit22=8'd22,
		bit23=8'd23,
		bit24=8'd24;

	
		
//generate sclk2
always@ (posedge clock or negedge reset)
begin
	if(!reset)
	begin
	clk_cnt<=0;
	clk_cnt2<=0;
	end
	else  
	begin
		if(clk_cnt==(present_cnt-1))
			begin
			clk_cnt<=0;
			clk_cnt2<=1;
			//sclk2=~sclk2;
			end
		else
			begin
			clk_cnt<=clk_cnt+1;
			clk_cnt2<=0;
			end
	end
end


always @*//(posedge clk_cnt2 or negedge reset)
if(!reset)
sclk2<=0;
else
sclk2<=~sclk2;

always @(posedge sclk2 or negedge reset)
	begin
		if(!reset)
			begin
			cs<=1;
			sclk<=1;
			cs_num<=0;
			end
		else
		begin
		if(cs_num<3)
			begin
			cs<=0;
			sclk<=1;
			cs_num<=cs_num+1;
			end
			else if((cs_num>=3) &(cs_num<=50))
			begin
			sclk<=~sclk;
			cs<=0;
			cs_num<=cs_num+1;
			end
		  else
			begin
			sclk<=1;
			cs_num<=51;
			cs<=1;
			end
		end
	end

initial
begin
command[0]<=		16'he3;		data[0]<=16'h3008;
command[1]<=		16'he7;		data[1]<=16'h0012;
command[2]<=		16'hef;		data[2]<=16'h1231;
command[3]<=		16'h00;		data[3]<=16'h0001;
command[4]<=		16'h01;		data[4]<=16'h0100;
command[5]<=		16'h02;		data[5]<=16'h0700;
command[6]<=		16'h03;		data[6]<=16'h1030;
command[7]<=		16'h04;		data[7]<=16'h0000;
command[8]<=		16'h08;		data[8]<=16'h0402;
command[9]<=		16'h09;		data[9]<=16'h0000;
command[10]<=		16'h0a;		data[10]<=16'h0008;
command[11]<=		16'h0c;		data[11]<=16'h0110;
command[12]<=		16'h0f;		data[12]<=16'h0002;
command[13]<=		16'h10;		data[13]<=16'h0000;
command[14]<=		16'h11;		data[14]<=16'h0007;
command[15]<=		16'h12;		data[15]<=16'h0000;
command[16]<=		16'h13;		data[16]<=16'h0000;
command[17]<=		16'h10;		data[17]<=16'h1190;
command[18]<=		16'h11;		data[18]<=16'h0227;
command[19]<=		16'h12;		data[19]<=16'h001c;
command[20]<=		16'h13;		data[20]<=16'h1200;
command[21]<=		16'h29;		data[21]<=16'h0025;
command[22]<=		16'h2b;		data[22]<=16'h0009;
command[23]<=		16'h30;		data[23]<=16'h0100;
command[24]<=		16'h31;		data[24]<=16'h0408;
command[25]<=		16'h32;		data[25]<=16'h0000;
command[26]<=		16'h35;		data[26]<=16'h0103;
command[27]<=		16'h36;		data[27]<=16'h1604;
command[28]<=		16'h37;		data[28]<=16'h0305;
command[29]<=		16'h38;		data[29]<=16'h0004;
command[30]<=		16'h39;		data[30]<=16'h0807;
command[31]<=		16'h3c;		data[31]<=16'h0401;
command[32]<=		16'h3d;		data[32]<=16'h000a;
command[33]<=		16'h50;		data[33]<=16'h0000;
command[34]<=		16'h51;		data[34]<=16'h00ef;
command[35]<=		16'h52;		data[35]<=16'h0000;
command[36]<=		16'h53;		data[36]<=16'h013f;
command[37]<=		16'h60;		data[37]<=16'ha700;
command[38]<=		16'h61;		data[38]<=16'h0001;
command[39]<=		16'h6a;		data[39]<=16'h0000;
command[40]<=		16'h80;		data[40]<=16'h0000;
command[41]<=		16'h81;		data[41]<=16'h0000;
command[42]<=		16'h82;		data[42]<=16'h0000;
command[43]<=		16'h83;		data[43]<=16'h0000;
command[44]<=		16'h84;		data[44]<=16'h0000;
command[45]<=		16'h85;		data[45]<=16'h0000;
command[46]<=		16'h90;		data[46]<=16'h0010;
command[47]<=		16'h92;		data[47]<=16'h0000;
command[48]<=		16'h93;		data[48]<=16'h0003;
command[49]<=		16'h95;		data[49]<=16'h0110;
command[50]<=		16'h97;		data[50]<=16'h0000;
command[51]<=		16'h98;		data[51]<=16'h0000;
command[52]<=		16'h07;		data[52]<=16'h0133;
end


always @(negedge sclk2 or negedge reset)
begin
	if (!reset)
		begin
		state<=bit1;
		sdi<=1;
	
		end
	else begin
		case(state)
	/*	ready: 
			begin
				state<=bit1;
				sdi<=1;
			end
			else
			begin
				state<=ready;
				sdi<=1;
			end
	*/
		bit1:if(!sclk)
			begin state<=bit2;
				sdi<=0;
			end
			else begin
			state<=bit1;
			sdi<=1;
			end
		bit2:if(!sclk)
			begin state<=bit3;
				sdi<=1;
			end
			else
			begin
			state<=bit2;
			sdi<=1;
			end
		bit3:if(!sclk)
			begin state<=bit4;
				sdi<=1;
			end
			else
			begin
			state<=bit3;
			sdi<=1;
			end
		bit4:if(!sclk)
			begin state<=bit5;
				sdi<=0;
			end
			else 
			begin
			state<=bit4;
			sdi<=1;
			end
		bit5:if(!sclk)
			begin state<=bit6;
				sdi<=0;
			end
			else state<=bit5;
		bit6:if(!sclk)
			begin state<=bit7;
				sdi=0;
			end
			else state<=bit6;
		bit7:if(!sclk)
			begin state<=bit8;
				if(flag_command)
				sdi=0;
				else
				sdi=1;
			end
			else state<=bit7;
		bit8:if(!sclk)
			begin state<=bit9;
				if(!flag_inverse)
				sdi<=0;
				else
				sdi<=1;
			end
			else 
			begin
			state<=bit8;
			sdi<=1;
			end
			
			
		bit9:if(!sclk)
			begin state<=bit10;
				sdi=data_tmp[15];
			end
			else state<=bit9;
		bit10:if(!sclk)
			begin state<=bit11;
				sdi=data_tmp[14];
			end
			else state<=bit10;
		bit11:if(!sclk)
			begin state<=bit12;
				sdi=data_tmp[13];
			end
			else state<=bit11;
		bit12:if(!sclk)
			begin state<=bit13;
				sdi=data_tmp[12];
			end
			else state<=bit12;
		bit13:if(!sclk)
			begin state<=bit14;
				sdi=data_tmp[11];
			end
			else state<=bit13;
		bit14:if(!sclk)
			begin state<=bit15;
				sdi=data_tmp[10];
			end
			else state<=bit14;
		bit15:if(!sclk)
			begin state<=bit16;
				sdi=data_tmp[9];
			end
			else state<=bit15;
		bit16:if(!sclk)
			begin state<=bit17;
				sdi=data_tmp[8];
			end
			else state<=bit16;
		bit17:if(!sclk)
			begin state<=bit18;
				sdi=data_tmp[7];
			end
			else state<=bit17;
		bit18:if(!sclk)
			begin state<=bit19;
				sdi=data_tmp[6];
			end
			else state<=bit18;
		bit19:if(!sclk)
			begin state<=bit20;
				sdi=data_tmp[5];
			end
			else state<=bit19;
		bit20:if(!sclk)
			begin state<=bit21;
				sdi=data_tmp[4];
			end
			else state<=bit20;
		bit21:if(!sclk)
			begin state<=bit22;
				sdi=data_tmp[3];
			end
			else state<=bit21;
		bit22:if(!sclk)
			begin state<=bit23;
				sdi=data_tmp[2];
			end
			else state<=bit22;
		bit23:if(!sclk)
			begin state<=bit24;
				sdi=data_tmp[1];
			end
			else state<=bit23;
		bit24:if(!sclk)
			begin state<=ready;
				sdi=data_tmp[0];
				
			end
			else
			begin
				state<=bit24;
				sdi=data_tmp[1];
			//		cs<=1;
			end
		default:begin
			state<=bit1;
			sdi<=1;
			end
		endcase	
	end
end


always@(negedge cs or negedge reset)
	if (!reset)
		begin
		init_num<=0;
		data_tmp<=command[0];
		flag_inverse<=0;
		end
	else begin
		case(init_num)
		0:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		1:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		2:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		3:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		4:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		5:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		6:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		7:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		8:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		9:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		10:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		11:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		12:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		13:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		14:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		15:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		16:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		17:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		18:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		19:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		20:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		21:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		22:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		23:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		24:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		25:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		26:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end
		
		27:
		begin
		if(!flag_inverse)
			begin
				data_tmp<=command[0];
				flag_inverse<=1;
				init_num<=0;
			end
		else
			begin
				data_tmp<=data[0];
				flag_inverse<=1;
				init_num<=1;
			end
		end