lcd_283rb06.hier_info

液晶显示驱动源程序代码

|lcd_283rb06
cs <= cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
sclk <= sclk~reg0.DB_MAX_OUTPUT_PORT_TYPE
sdi <= sdi~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock => reset.CLK
clock => count_reset[3].CLK
clock => count_reset[2].CLK
clock => count_reset[1].CLK
clock => count_reset[0].CLK
clock => sck_count[1].CLK
clock => sck_count[0].CLK
clock => cs~reg0.CLK
clock => sclk~reg0.CLK
clock => bit_transfered[24].CLK
clock => bit_transfered[23].CLK
clock => bit_transfered[22].CLK
clock => bit_transfered[21].CLK
clock => bit_transfered[20].CLK
clock => bit_transfered[19].CLK
clock => bit_transfered[18].CLK
clock => bit_transfered[17].CLK
clock => bit_transfered[16].CLK
clock => bit_transfered[15].CLK
clock => bit_transfered[14].CLK
clock => bit_transfered[13].CLK
clock => bit_transfered[12].CLK
clock => bit_transfered[11].CLK
clock => bit_transfered[10].CLK
clock => bit_transfered[9].CLK
clock => bit_transfered[8].CLK
clock => bit_transfered[7].CLK
clock => bit_transfered[6].CLK
clock => bit_transfered[5].CLK
clock => bit_transfered[4].CLK
clock => bit_transfered[3].CLK
clock => bit_transfered[2].CLK
clock => bit_transfered[1].CLK
clock => bit_transfered[0].CLK
clock => sdi~reg0.CLK
clock => i[5].CLK
clock => i[4].CLK
clock => i[3].CLK
clock => i[2].CLK
clock => i[1].CLK
clock => i[0].CLK
clock => state_dclk[1].CLK
clock => state_dclk[0].CLK
clock => count1[20].CLK
clock => count1[19].CLK
clock => count1[18].CLK
clock => count1[17].CLK
clock => count1[16].CLK
clock => count1[15].CLK
clock => count1[14].CLK
clock => count1[13].CLK
clock => count1[12].CLK
clock => count1[11].CLK
clock => count1[10].CLK
clock => count1[9].CLK
clock => count1[8].CLK
clock => count1[7].CLK
clock => count1[6].CLK
clock => count1[5].CLK
clock => count1[4].CLK
clock => count1[3].CLK
clock => count1[2].CLK
clock => count1[1].CLK
clock => count1[0].CLK
clock => count0[20].CLK
clock => count0[19].CLK
clock => count0[18].CLK
clock => count0[17].CLK
clock => count0[16].CLK
clock => count0[15].CLK
clock => count0[14].CLK
clock => count0[13].CLK
clock => count0[12].CLK
clock => count0[11].CLK
clock => count0[10].CLK
clock => count0[9].CLK
clock => count0[8].CLK
clock => count0[7].CLK
clock => count0[6].CLK
clock => count0[5].CLK
clock => count0[4].CLK
clock => count0[3].CLK
clock => count0[2].CLK
clock => count0[1].CLK
clock => count0[0].CLK
clock => sw1_out1_reg.CLK
clock => count1_4[20].CLK
clock => count1_4[19].CLK
clock => count1_4[18].CLK
clock => count1_4[17].CLK
clock => count1_4[16].CLK
clock => count1_4[15].CLK
clock => count1_4[14].CLK
clock => count1_4[13].CLK
clock => count1_4[12].CLK
clock => count1_4[11].CLK
clock => count1_4[10].CLK
clock => count1_4[9].CLK
clock => count1_4[8].CLK
clock => count1_4[7].CLK
clock => count1_4[6].CLK
clock => count1_4[5].CLK
clock => count1_4[4].CLK
clock => count1_4[3].CLK
clock => count1_4[2].CLK
clock => count1_4[1].CLK
clock => count1_4[0].CLK
clock => count0_4[20].CLK
clock => count0_4[19].CLK
clock => count0_4[18].CLK
clock => count0_4[17].CLK
clock => count0_4[16].CLK
clock => count0_4[15].CLK
clock => count0_4[14].CLK
clock => count0_4[13].CLK
clock => count0_4[12].CLK
clock => count0_4[11].CLK
clock => count0_4[10].CLK
clock => count0_4[9].CLK
clock => count0_4[8].CLK
clock => count0_4[7].CLK
clock => count0_4[6].CLK
clock => count0_4[5].CLK
clock => count0_4[4].CLK
clock => count0_4[3].CLK
clock => count0_4[2].CLK
clock => count0_4[1].CLK
clock => count0_4[0].CLK
clock => sw4_out1_reg.CLK
clock => pic_tmp[0].CLK
clock => pic_tmp[1].CLK
clock => pic_tmp[2].CLK
clock => pic_tmp[3].CLK
clock => pic_tmp[4].CLK
clock => pic_num[0].CLK
clock => pic_num[1].CLK
clock => pic_num[2].CLK
clock => pic_num[3].CLK
clock => pic_num[4].CLK
clock => pic_num[5].CLK
clock => able.CLK
clock => number[0].CLK
clock => number[1].CLK
clock => number[2].CLK
clock => number[3].CLK
clock => number[4].CLK
clock => number[5].CLK
clock => number[6].CLK
clock => number[7].CLK
clock => number[8].CLK
clock => number[9].CLK
clock => number[10].CLK
clock => number[11].CLK
clock => number[12].CLK
clock => number[13].CLK
clock => number[14].CLK
clock => number[15].CLK
clock => count[0].CLK
clock => count[1].CLK
clock => count[2].CLK
clock => count[3].CLK
clock => count[4].CLK
clock => count[5].CLK
clock => count[6].CLK
clock => count[7].CLK
clock => count[8].CLK
clock => count[9].CLK
clock => count[10].CLK
clock => count[11].CLK
clock => count[12].CLK
clock => count[13].CLK
clock => count[14].CLK
clock => count[15].CLK
clock => id_data_cmd[0].CLK
clock => id_data_cmd[1].CLK
clock => id_data_cmd[2].CLK
clock => id_data_cmd[3].CLK
clock => id_data_cmd[4].CLK
clock => id_data_cmd[5].CLK
clock => id_data_cmd[6].CLK
clock => id_data_cmd[7].CLK
clock => data_temp[0].CLK
clock => data_temp[1].CLK
clock => data_temp[2].CLK
clock => data_temp[3].CLK
clock => data_temp[4].CLK
clock => data_temp[5].CLK
clock => data_temp[6].CLK
clock => data_temp[7].CLK
clock => data_temp[8].CLK
clock => data_temp[9].CLK
clock => data_temp[10].CLK
clock => data_temp[11].CLK
clock => data_temp[12].CLK
clock => data_temp[13].CLK
clock => data_temp[14].CLK
clock => data_temp[15].CLK
clock => j[0].CLK
clock => j[1].CLK
clock => j[2].CLK
clock => j[3].CLK
clock => j[4].CLK
clock => j[5].CLK
clock => j[6].CLK
clock => A[20]~reg0.CLK
clock => A[19]~reg0.CLK
clock => A[18]~reg0.CLK
clock => A[17]~reg0.CLK
clock => A[16]~reg0.CLK
clock => A[15]~reg0.CLK
clock => A[14]~reg0.CLK
clock => A[13]~reg0.CLK
clock => A[12]~reg0.CLK
clock => A[11]~reg0.CLK
clock => A[10]~reg0.CLK
clock => A[9]~reg0.CLK
clock => A[8]~reg0.CLK
clock => A[7]~reg0.CLK
clock => A[6]~reg0.CLK
clock => A[5]~reg0.CLK
clock => A[4]~reg0.CLK
clock => A[3]~reg0.CLK
clock => A[2]~reg0.CLK
clock => A[1]~reg0.CLK
clock => A[0]~reg0.CLK
clock => oe~reg0.CLK
clock => ce1~reg0.CLK
clock => ce2~reg0.CLK
clock => ce3~reg0.CLK
clock => red[5]~en.CLK
clock => red[5]~reg0.CLK
clock => red[4]~en.CLK
clock => red[4]~reg0.CLK
clock => red[3]~en.CLK
clock => red[3]~reg0.CLK
clock => red[2]~en.CLK
clock => red[2]~reg0.CLK
clock => red[1]~en.CLK
clock => red[1]~reg0.CLK
clock => red[0]~en.CLK
clock => red[0]~reg0.CLK
clock => green[5]~en.CLK
clock => green[5]~reg0.CLK
clock => green[4]~en.CLK
clock => green[4]~reg0.CLK
clock => green[3]~en.CLK
clock => green[3]~reg0.CLK
clock => green[2]~en.CLK
clock => green[2]~reg0.CLK
clock => green[1]~en.CLK
clock => green[1]~reg0.CLK
clock => green[0]~en.CLK
clock => green[0]~reg0.CLK
clock => blue[5]~en.CLK
clock => blue[5]~reg0.CLK
clock => blue[4]~en.CLK
clock => blue[4]~reg0.CLK
clock => blue[3]~en.CLK
clock => blue[3]~reg0.CLK
clock => blue[2]~en.CLK
clock => blue[2]~reg0.CLK
clock => blue[1]~en.CLK
clock => blue[1]~reg0.CLK
clock => blue[0]~en.CLK
clock => blue[0]~reg0.CLK
clock => we~reg0.CLK
clock => db21~en.CLK
clock => db21~reg0.CLK
clock => db20~en.CLK
clock => db20~reg0.CLK
clock => db19~en.CLK
clock => db19~reg0.CLK
clock => db18~en.CLK
clock => db18~reg0.CLK
clock => state~17.IN1
clock => main_state~0.IN1
hsync <= hsync~reg0.DB_MAX_OUTPUT_PORT_TYPE
vsync <= vsync~reg0.DB_MAX_OUTPUT_PORT_TYPE
enable <= enable~reg0.DB_MAX_OUTPUT_PORT_TYPE
dotclk <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
rd <= <VCC>
red[0] <= red[0]~12
red[1] <= red[1]~11
red[2] <= red[2]~10
red[3] <= red[3]~8
red[4] <= red[4]~3
red[5] <= red[5]~1
green[0] <= green[0]~5
green[1] <= green[1]~4
green[2] <= green[2]~3
green[3] <= green[3]~2
green[4] <= green[4]~1
green[5] <= green[5]~0
blue[0] <= blue[0]~5
blue[1] <= blue[1]~4
blue[2] <= blue[2]~3
blue[3] <= blue[3]~2
blue[4] <= blue[4]~1
blue[5] <= blue[5]~0
A[0] <= A[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[1] <= A[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[2] <= A[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[3] <= A[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[4] <= A[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[5] <= A[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[6] <= A[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[7] <= A[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[8] <= A[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[9] <= A[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[10] <= A[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[11] <= A[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[12] <= A[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[13] <= A[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[14] <= A[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[15] <= A[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[16] <= A[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[17] <= A[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[18] <= A[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[19] <= A[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
A[20] <= A[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sw2 => count1_4~20.OUTPUTSELECT
sw2 => count1_4~19.OUTPUTSELECT
sw2 => count1_4~18.OUTPUTSELECT
sw2 => count1_4~17.OUTPUTSELECT
sw2 => count1_4~16.OUTPUTSELECT
sw2 => count1_4~15.OUTPUTSELECT
sw2 => count1_4~14.OUTPUTSELECT
sw2 => count1_4~13.OUTPUTSELECT
sw2 => count1_4~12.OUTPUTSELECT
sw2 => count1_4~11.OUTPUTSELECT
sw2 => count1_4~10.OUTPUTSELECT
sw2 => count1_4~9.OUTPUTSELECT
sw2 => count1_4~8.OUTPUTSELECT
sw2 => count1_4~7.OUTPUTSELECT
sw2 => count1_4~6.OUTPUTSELECT
sw2 => count1_4~5.OUTPUTSELECT
sw2 => count1_4~4.OUTPUTSELECT
sw2 => count1_4~3.OUTPUTSELECT
sw2 => count1_4~2.OUTPUTSELECT
sw2 => count1_4~1.OUTPUTSELECT
sw2 => count1_4~0.OUTPUTSELECT
sw2 => count0_4~20.OUTPUTSELECT
sw2 => count0_4~19.OUTPUTSELECT
sw2 => count0_4~18.OUTPUTSELECT
sw2 => count0_4~17.OUTPUTSELECT
sw2 => count0_4~16.OUTPUTSELECT
sw2 => count0_4~15.OUTPUTSELECT
sw2 => count0_4~14.OUTPUTSELECT
sw2 => count0_4~13.OUTPUTSELECT
sw2 => count0_4~12.OUTPUTSELECT
sw2 => count0_4~11.OUTPUTSELECT
sw2 => count0_4~10.OUTPUTSELECT
sw2 => count0_4~9.OUTPUTSELECT
sw2 => count0_4~8.OUTPUTSELECT
sw2 => count0_4~7.OUTPUTSELECT
sw2 => count0_4~6.OUTPUTSELECT
sw2 => count0_4~5.OUTPUTSELECT
sw2 => count0_4~4.OUTPUTSELECT
sw2 => count0_4~3.OUTPUTSELECT
sw2 => count0_4~2.OUTPUTSELECT
sw2 => count0_4~1.OUTPUTSELECT
sw2 => count0_4~0.OUTPUTSELECT
ce1 <= ce1~reg0.DB_MAX_OUTPUT_PORT_TYPE
ce2 <= ce2~reg0.DB_MAX_OUTPUT_PORT_TYPE
ce3 <= ce3~reg0.DB_MAX_OUTPUT_PORT_TYPE
oe <= oe~reg0.DB_MAX_OUTPUT_PORT_TYPE
we <= we~reg0.DB_MAX_OUTPUT_PORT_TYPE
sw1 => count1~20.OUTPUTSELECT
sw1 => count1~19.OUTPUTSELECT
sw1 => count1~18.OUTPUTSELECT
sw1 => count1~17.OUTPUTSELECT
sw1 => count1~16.OUTPUTSELECT
sw1 => count1~15.OUTPUTSELECT
sw1 => count1~14.OUTPUTSELECT
sw1 => count1~13.OUTPUTSELECT
sw1 => count1~12.OUTPUTSELECT
sw1 => count1~11.OUTPUTSELECT
sw1 => count1~10.OUTPUTSELECT
sw1 => count1~9.OUTPUTSELECT
sw1 => count1~8.OUTPUTSELECT
sw1 => count1~7.OUTPUTSELECT
sw1 => count1~6.OUTPUTSELECT
sw1 => count1~5.OUTPUTSELECT
sw1 => count1~4.OUTPUTSELECT
sw1 => count1~3.OUTPUTSELECT
sw1 => count1~2.OUTPUTSELECT
sw1 => count1~1.OUTPUTSELECT
sw1 => count1~0.OUTPUTSELECT
sw1 => count0~20.OUTPUTSELECT
sw1 => count0~19.OUTPUTSELECT
sw1 => count0~18.OUTPUTSELECT
sw1 => count0~17.OUTPUTSELECT
sw1 => count0~16.OUTPUTSELECT
sw1 => count0~15.OUTPUTSELECT
sw1 => count0~14.OUTPUTSELECT
sw1 => count0~13.OUTPUTSELECT
sw1 => count0~12.OUTPUTSELECT
sw1 => count0~11.OUTPUTSELECT
sw1 => count0~10.OUTPUTSELECT
sw1 => count0~9.OUTPUTSELECT
sw1 => count0~8.OUTPUTSELECT
sw1 => count0~7.OUTPUTSELECT
sw1 => count0~6.OUTPUTSELECT
sw1 => count0~5.OUTPUTSELECT
sw1 => count0~4.OUTPUTSELECT
sw1 => count0~3.OUTPUTSELECT
sw1 => count0~2.OUTPUTSELECT
sw1 => count0~1.OUTPUTSELECT
sw1 => count0~0.OUTPUTSELECT
sdao <= <UNC>
sclo <= <GND>
penirq => ~NO_FANOUT~
db18 <= db18~0
db19 <= db19~0
db20 <= db20~0
db21 <= db21~0