prev_cmp_lcd_283rb06.sim.qmsg

液晶显示驱动源程序代码

{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.delay_ACK_2 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.delay_ACK_2\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.AckYESNO_2 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.AckYESNO_2\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.delay3_2 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.delay3_2\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.delay1_3 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.delay1_3\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.sendData2 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.sendData2\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.sendbit1_3 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.sendbit1_3\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.delay2_3 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.delay2_3\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.sendbit2_3 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.sendbit2_3\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.ForACK1_3 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.ForACK1_3\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.delay_ACK_3 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.delay_ACK_3\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.AckYESNO_3 " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.AckYESNO_3\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.Stop " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.Stop\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.Finish_delay " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.Finish_delay\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|lcd_283rb06\|send_byte_zt.start " "Warning: Can't display state machine states -- register holding state machine bit \"\|lcd_283rb06\|send_byte_zt.start\" was synthesized away" {  } { { "lcd_init.v" "" { Text "C:/Documents and Settings/shuang_sun/My Documents/FPGA/2.83rb06/lcd_init.v" 1384 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[0\] Input Output " "Warning: Wrong node type for node \"red\[0\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[1\] Input Output " "Warning: Wrong node type for node \"red\[1\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[2\] Input Output " "Warning: Wrong node type for node \"red\[2\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[3\] Input Output " "Warning: Wrong node type for node \"red\[3\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[4\] Input Output " "Warning: Wrong node type for node \"red\[4\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "red\[5\] Input Output " "Warning: Wrong node type for node \"red\[5\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[0\] Input Output " "Warning: Wrong node type for node \"green\[0\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[1\] Input Output " "Warning: Wrong node type for node \"green\[1\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[2\] Input Output " "Warning: Wrong node type for node \"green\[2\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[3\] Input Output " "Warning: Wrong node type for node \"green\[3\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "green\[4\] Input Output " "Warning: Wrong node type for node \"green\[4\]\" in vector source file. Design node is of type Input, but signal in vector source file is of type Output." {  } {  } 0 0 "Wrong node type for node \"%1!s!\" in vector source file. Design node is of type %2!s!, but signal in vector source file is of type %3!s!." 0 0 "" 0}