prev_cmp_lcd_283rb06.map.qmsg

液晶显示驱动源程序代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 24 13:12:21 2008 " "Info: Processing started: Wed Sep 24 13:12:21 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd_283rb06 -c lcd_283rb06 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_283rb06 -c lcd_283rb06" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(529) " "Warning (10273): Verilog HDL warning at lcd_init.v(529): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 529 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(530) " "Warning (10273): Verilog HDL warning at lcd_init.v(530): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 530 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(531) " "Warning (10273): Verilog HDL warning at lcd_init.v(531): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 531 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(755) " "Warning (10273): Verilog HDL warning at lcd_init.v(755): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 755 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(756) " "Warning (10273): Verilog HDL warning at lcd_init.v(756): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 756 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(757) " "Warning (10273): Verilog HDL warning at lcd_init.v(757): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 757 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(777) " "Warning (10273): Verilog HDL warning at lcd_init.v(777): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 777 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(778) " "Warning (10273): Verilog HDL warning at lcd_init.v(778): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 778 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "lcd_init.v(779) " "Warning (10273): Verilog HDL warning at lcd_init.v(779): extended using \"x\" or \"z\"" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 779 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcd_init.v(520) " "Warning (10268): Verilog HDL information at lcd_init.v(520): Always Construct contains both blocking and non-blocking assignments" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 520 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "lcd_init.v(1734) " "Warning (10090): Verilog HDL syntax warning at lcd_init.v(1734): extra block comment delimiter characters /* within block comment" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1734 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "lcd_init.v(1740) " "Warning (10090): Verilog HDL syntax warning at lcd_init.v(1740): extra block comment delimiter characters /* within block comment" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1740 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "lcd_init.v(1879) " "Warning (10090): Verilog HDL syntax warning at lcd_init.v(1879): extra block comment delimiter characters /* within block comment" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1879 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "lcd_init.v(1924) " "Warning (10090): Verilog HDL syntax warning at lcd_init.v(1924): extra block comment delimiter characters /* within block comment" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1924 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "lcd_init.v(1947) " "Warning (10090): Verilog HDL syntax warning at lcd_init.v(1947): extra block comment delimiter characters /* within block comment" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1947 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_EXTRA_SLASH_STAR" "lcd_init.v(1978) " "Warning (10090): Verilog HDL syntax warning at lcd_init.v(1978): extra block comment delimiter characters /* within block comment" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1978 0 0 } }  } 0 10090 "Verilog HDL syntax warning at %1!s!: extra block comment delimiter characters /* within block comment" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_init.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_init.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_283rb06 " "Info: Found entity 1: lcd_283rb06" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd_283rb06 " "Info: Elaborating entity \"lcd_283rb06\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "test lcd_init.v(89) " "Warning (10036): Verilog HDL or VHDL warning at lcd_init.v(89): object \"test\" assigned a value but never read" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 89 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "measure_time lcd_init.v(449) " "Warning (10036): Verilog HDL or VHDL warning at lcd_init.v(449): object \"measure_time\" assigned a value but never read" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 449 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "touch_time lcd_init.v(505) " "Warning (10036): Verilog HDL or VHDL warning at lcd_init.v(505): object \"touch_time\" assigned a value but never read" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 505 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "delay_measure_count lcd_init.v(506) " "Warning (10036): Verilog HDL or VHDL warning at lcd_init.v(506): object \"delay_measure_count\" assigned a value but never read" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 506 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 lcd_init.v(102) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(102): truncated value with size 32 to match size of target (4)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 102 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 lcd_init.v(107) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(107): truncated value with size 32 to match size of target (4)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "main_state lcd_init.v(190) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(190): variable \"main_state\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 190 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sck_count lcd_init.v(194) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(194): variable \"sck_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 194 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "bit_transfered lcd_init.v(199) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(199): variable \"bit_transfered\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 199 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sck_count lcd_init.v(199) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(199): variable \"sck_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 199 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "sck_count lcd_init.v(204) " "Warning (10235): Verilog HDL Always Construct warning at lcd_init.v(204): variable \"sck_count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 204 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd_init.v(354) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(354): truncated value with size 32 to match size of target (7)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 354 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}