lcd_283rb06.map.qmsg

液晶显示驱动源程序代码

{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rd lcd_init.v(290) " "Warning (10240): Verilog HDL Always Construct warning at lcd_init.v(290): inferring latch(es) for variable \"rd\", which holds its previous value in one or more paths through the always construct" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 290 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 lcd_init.v(403) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(403): truncated value with size 3 to match size of target (2)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 403 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 lcd_init.v(410) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(410): truncated value with size 3 to match size of target (2)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 410 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 lcd_init.v(413) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(413): truncated value with size 3 to match size of target (2)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 413 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 lcd_init.v(418) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(418): truncated value with size 3 to match size of target (2)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 418 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 lcd_init.v(423) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(423): truncated value with size 3 to match size of target (2)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 423 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 lcd_init.v(427) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(427): truncated value with size 3 to match size of target (2)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 427 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "lcd_init.v(430) " "Warning (10199): Verilog HDL Case Statement warning at lcd_init.v(430): case item expression never matches the case expression" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 430 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 lcd_init.v(460) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(460): truncated value with size 32 to match size of target (10)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 460 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 lcd_init.v(472) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(472): truncated value with size 32 to match size of target (10)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 472 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(728) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(728): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 728 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(729) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(729): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 729 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(730) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(730): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 730 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(753) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(753): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 753 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(754) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(754): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 754 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(755) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(755): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 755 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(784) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(784): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 784 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 17 lcd_init.v(1259) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1259): truncated value with size 21 to match size of target (17)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1259 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 lcd_init.v(1263) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1263): truncated value with size 32 to match size of target (17)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1263 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 17 lcd_init.v(1275) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1275): truncated value with size 32 to match size of target (17)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1275 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "21 17 lcd_init.v(1277) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1277): truncated value with size 21 to match size of target (17)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1277 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(1308) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1308): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1308 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(1316) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1316): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1316 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(1345) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1345): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1345 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 lcd_init.v(1356) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1356): truncated value with size 32 to match size of target (21)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1356 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 lcd_init.v(1385) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1385): truncated value with size 32 to match size of target (4)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1385 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 lcd_init.v(1400) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1400): truncated value with size 32 to match size of target (4)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1400 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 lcd_init.v(1410) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1410): truncated value with size 32 to match size of target (5)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1410 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd_init.v(1412) " "Warning (10230): Verilog HDL assignment warning at lcd_init.v(1412): truncated value with size 32 to match size of target (6)" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 1412 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "command\[22\]\[15\] 0 lcd_init.v(37) " "Warning (10030): Net \"command\[22\]\[15\]\" at lcd_init.v(37) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 37 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "command\[22\]\[14\] 0 lcd_init.v(37) " "Warning (10030): Net \"command\[22\]\[14\]\" at lcd_init.v(37) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 37 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "command\[22\]\[13\] 0 lcd_init.v(37) " "Warning (10030): Net \"command\[22\]\[13\]\" at lcd_init.v(37) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 37 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "command\[22\]\[12\] 0 lcd_init.v(37) " "Warning (10030): Net \"command\[22\]\[12\]\" at lcd_init.v(37) has no driver or initial value, using a default initial value '0'" {  } { { "lcd_init.v" "" { Text "D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_init.v" 37 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}