lcd_init_0504.v.bak

液晶显示驱动源程序代码

module lcd_283rb06(cs,sclk,sdi,reset,clock);
output cs;
output sclk;
output sdi;
input reset;
input clock;  //25MHz (39.6ns)
reg [1:0] sck_count;
reg [8:0] bit_transfered;
reg [7:0] data_to_send;
reg [7:0] data_received;  

reg [4:0] main_state,next_state;
parameter IDLE=5'b0_0001,
		  START=5'b0_0010,
		  INSTRUCTION=5'b0_0100,
		  DATA=5'b0_1000,
		  STOP=5'b1_0000;
integer i;


always @(posedge clock or negedge reset)
	if (!reset)
		main_state<=IDLE;
	else
		main_state<=next_state;
		
always @*
begin
	case(main_state)
	IDLE:
		next_state=START;
	START:
		if(sck_count==1)
			next_state=INSTRUCTION;
		else
			next_state=START;
	INSTRUCTION:
		if(bit_transfered[8]==1)
			next_state=DATA;
		else
			next_state=INSTRUCTION;
	DATA:
		if(bit_transfered[7]==1 && sck_count==1)
			next_state=STOP;
		else
			next_state=DATA;
	STOP:
		if(sck_count==1)
			next_state=IDLE;
		else
			next_state=STOP;
	default:
		next_state=IDLE;
	endcase
end

always @(posedge clock)
	if(main_state==IDLE)
		sck_count<=0;
	else
		sck_count<=sck_count+1;
		
always @(posedge clock)
	if(main_state==IDLE)
		cs<=1;
	else if(main_state==START && sck_count==1)
		cs<=0;
	else if(main_state==STOP && sck_count==2)
		cs<=1;
		
always @(posedge clock)
	if(main_state==IDLE||main_state==STOP)
		sclk<=1;
	else if(sck_count==2)
		sclk<=0;
	else if(sck_count==0)
		sclk<=1;
		
always @(posedge clock)
	if (main_state==INSTRUCTION && bit_transfered[0]==1)
	begin
		if(read_flag==0)
			data_to_send<={3'b0,waddr};
		else
			data_to_send<={3'b100,waddr};
	end
	else if(main_state==DATA && bit_transfered[8]==1)
		data_to_send<=wdata;
	else if(sck_count==2)
		data_to_send<={data_to_send[6:0],1'b0};
		
assign sdi=data_to_send[7];

//传输比特计数
always @(posedge clock)
	if(main_state==IDLE)
		bit_transfered<=9'b0;
	else if(main_state==START)
		bit_transfered<=9'b0_0000_0001;
	else if(sck_count==0)
		bit_transfered<={bit_transfered[7:0],bit_transfered[8]};
		
/*		
task Send_Instruction;
begin
	repeat(8)
	begin
		@(posedge sclk)
		if(lsb_first==0)
			data_temp={data_temp[6:0],spi_sdio};
		else
			data_temp={spi_sdio,data_temp[7:1]};
	end
	instruction=data_temp[7];
	addr=data_temp[4:0];
end
endtask
*/

task Send_Data;
begin
	for(i=0;i<8;i=i+1)
	begin
		@(negedge sclk)
		if(lsb_first==0)
			spi_sdo=register[addr][7-i];
		else
			spi_sdo=register[assr][i];
	end
end
endtask

task Send_Command;
begin
	for(i=0;i<8;i=i+1)
	begin
		@(negedge sclk)
		if(lsb_first==0)
			spi_sdo=register[addr][7-i];
		else
			spi_sdo=register[assr][i];
	end
end
endtask

always @(negedge cs)
begin
	Send_Data;
	Send_Command;
end
endmodule