lcd_283rb06.fit.rpt

液晶显示驱动源程序代码

; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/2.83/new edition fpga rgb/2.83RD05_FPGA/lcd_283rb06.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 788 / 4,608 ( 17 % ) ;
;     -- Combinational with no register       ; 526                  ;
;     -- Register only                        ; 2                    ;
;     -- Combinational with a register        ; 260                  ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 292                  ;
;     -- 3 input functions                    ; 145                  ;
;     -- <=2 input functions                  ; 349                  ;
;     -- Register only                        ; 2                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 539                  ;
;     -- arithmetic mode                      ; 247                  ;
;                                             ;                      ;
; Total registers*                            ; 262 / 4,851 ( 5 % )  ;
;     -- Dedicated logic registers            ; 262 / 4,608 ( 6 % )  ;
;     -- I/O registers                        ; 0 / 243 ( 0 % )      ;
;                                             ;                      ;
; Total LABs:  partially or completely used   ; 64 / 288 ( 22 % )    ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 64 / 89 ( 72 % )     ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )       ;
; Global signals                              ; 5                    ;
; M4Ks                                        ; 0 / 26 ( 0 % )       ;
; Total memory bits                           ; 0 / 119,808 ( 0 % )  ;
; Total RAM block bits                        ; 0 / 119,808 ( 0 % )  ;
; Embedded Multiplier 9-bit elements          ; 0 / 26 ( 0 % )       ;
; PLLs                                        ; 0 / 2 ( 0 % )        ;
; Global clocks                               ; 5 / 8 ( 63 % )       ;
; Average interconnect usage                  ; 3%                   ;
; Peak interconnect usage                     ; 4%                   ;
; Maximum fan-out node                        ; clock~clkctrl        ;
; Maximum fan-out                             ; 227                  ;
; Highest non-global fan-out signal           ; j[5]                 ;
; Highest non-global fan-out                  ; 52                   ;
; Total fan-out                               ; 3320                 ;
; Average fan-out                             ; 2.96                 ;
+---------------------------------------------+----------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.