sin

使用VHDL语言和CPLD芯片生成39KHz的信号

--                  1       2       4       8       16      32  
--                  30      15      7.5     3.75    1.875   0.9375
--  78.125          384     192     96      48      24      12
--  62.5    4       480     240     120     60      30      15
--  46.875  3       640     320     160     80      40      20
--  39.0625 2       768     384     192     96      48      24
--  31.25   1       960     480     240     120     60      30
--  23.4375         1280    640     320     160     80      40


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY SIN IS
   PORT (CLK:               IN Std_logic;       --输入时钟--

		Set_Freq_IN:   		IN Std_logic_vector(4 DOWNTO 1) := "0000"; 	--频率控制--

        Signal_Freq_Out:    INOUT Std_logic;    --输出频率--
        Signal_RUN_DIS:  	INOUT Std_logic    --输出频率--
        
        --VCC1:      			IN Std_logic;      
        --VCC2:      			IN Std_logic      
	);
END SIN ;

ARCHITECTURE using_std_logic OF SIN IS
	SIGNAL Set_Freq_OLD_IN:   	Std_logic_vector(4 DOWNTO 1) := "0000"; 	--频率控制--

    SIGNAL VAL_Freq_Set:    INTEGER RANGE 0 TO 511	:= 0;
    SIGNAL Count_Freq:    	INTEGER RANGE 0 TO 1023	:= 0;
    SIGNAL Count_Set_Freq:  INTEGER RANGE 0 TO 1023	:= 0;

    SIGNAL Count_RUN:    	INTEGER RANGE 0 TO 10100	:= 0;
    --SIGNAL Count_CLK:  		INTEGER RANGE 0 TO 1048575	:= 0;
BEGIN




--频率加按钮处理
   SET_VAL_Freq:PROCESS(CLK)
   BEGIN
        IF CLK'EVENT AND CLK='1' THEN
            IF Set_Freq_IN = Set_Freq_OLD_IN THEN               --频率加按钮信号为H--
				IF Count_Set_Freq < 1000 THEN
					Count_Set_Freq <= (Count_Set_Freq + 1); 	--频率加按钮H计数器加一--
				ELSE
            		IF Set_Freq_IN = "1111" THEN
                		VAL_Freq_Set <= (480-1);				--1#频率分频值--480/2--31.25
	            	ELSIF Set_Freq_IN = "1101" THEN              
		            	VAL_Freq_Set <= (384-1);				--2#频率分频值--384/2--39.0625--
					ELSIF Set_Freq_IN =  "1011" THEN               
              			VAL_Freq_Set <= (320-1);				--3#频率分频值--320/2--46.875--
                	ELSIF Set_Freq_IN =  "0111" THEN
                    		VAL_Freq_Set <= (240-1);				--4#频率分频值--240/2--62.5--
        			END IF;
				END IF;
			ELSE
				Count_Set_Freq <= 0;
				Set_Freq_OLD_IN <= Set_Freq_IN;
			END IF;
		END IF;
   END PROCESS SET_VAL_Freq;

--频率信号输出---
   OUT_Freq:PROCESS(CLK)
   BEGIN
        IF CLK'EVENT AND CLK='1' THEN
            Count_Freq <= Count_Freq + 1;
            IF Count_Freq >= VAL_Freq_Set THEN
                Signal_Freq_Out <= NOT Signal_Freq_Out;     	--输出频率--
				Count_Freq <= 0;
            END IF;
        END IF;
   END PROCESS OUT_Freq;

--RUN信号输出---
   RUN_DIS:PROCESS(Signal_Freq_Out)
   BEGIN
        IF Signal_Freq_Out'EVENT AND Signal_Freq_Out='1' THEN
            Count_RUN <= Count_RUN + 1;
            IF Count_RUN >= 10000 THEN
                Signal_RUN_DIS <= NOT Signal_RUN_DIS;     	--输出频率--
				Count_RUN <= 0;
            END IF;
        END IF;
   END PROCESS RUN_DIS;

END using_std_logic;