sin.fit.summary

使用VHDL语言和CPLD芯片生成39KHz的信号

Fitter Status : Successful - Mon Oct 27 16:51:12 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : SIN
Top-level Entity Name : SIN
Family : MAX II
Device : EPM240T100I5
Timing Models : Final
Total logic elements : 58 / 240 ( 24 % )
Total pins : 7 / 80 ( 9 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )