sin.fit.qmsg

使用VHDL语言和CPLD芯片生成39KHz的信号

{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.600 ns register register " "Info: Estimated most critical path is register to register delay of 10.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Count_Freq\[0\] 1 REG LAB_X4_Y3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 4; REG Node = 'Count_Freq\[0\]'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Count_Freq[0] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.200 ns) 1.757 ns LessThan1~459 2 COMB LAB_X3_Y3 1 " "Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~459'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.757 ns" { Count_Freq[0] LessThan1~459 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.511 ns) 2.937 ns LessThan1~460 3 COMB LAB_X3_Y3 1 " "Info: 3: + IC(0.669 ns) + CELL(0.511 ns) = 2.937 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~460'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan1~459 LessThan1~460 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.511 ns) 4.117 ns LessThan1~461 4 COMB LAB_X3_Y3 1 " "Info: 4: + IC(0.669 ns) + CELL(0.511 ns) = 4.117 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~461'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan1~460 LessThan1~461 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.511 ns) 5.297 ns LessThan1~462 5 COMB LAB_X3_Y3 1 " "Info: 5: + IC(0.669 ns) + CELL(0.511 ns) = 5.297 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~462'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan1~461 LessThan1~462 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.511 ns) 6.477 ns LessThan1~463 6 COMB LAB_X3_Y3 1 " "Info: 6: + IC(0.669 ns) + CELL(0.511 ns) = 6.477 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~463'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan1~462 LessThan1~463 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 7.657 ns LessThan1~464 7 COMB LAB_X3_Y3 11 " "Info: 7: + IC(0.440 ns) + CELL(0.740 ns) = 7.657 ns; Loc. = LAB_X3_Y3; Fanout = 11; COMB Node = 'LessThan1~464'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan1~463 LessThan1~464 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.183 ns) + CELL(1.760 ns) 10.600 ns Count_Freq\[7\] 8 REG LAB_X4_Y3 4 " "Info: 8: + IC(1.183 ns) + CELL(1.760 ns) = 10.600 ns; Loc. = LAB_X4_Y3; Fanout = 4; REG Node = 'Count_Freq\[7\]'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { LessThan1~464 Count_Freq[7] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.744 ns ( 44.75 % ) " "Info: Total cell delay = 4.744 ns ( 44.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.856 ns ( 55.25 % ) " "Info: Total interconnect delay = 5.856 ns ( 55.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "10.600 ns" { Count_Freq[0] LessThan1~459 LessThan1~460 LessThan1~461 LessThan1~462 LessThan1~463 LessThan1~464 Count_Freq[7] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "2 " "Warning: Following 2 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "Signal_Freq_Out a permanently enabled " "Info: Pin Signal_Freq_Out has a permanently enabled output enable" {  } { { "d:/quartus ii 7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartus ii 7.2/quartus/bin/pin_planner.ppl" { Signal_Freq_Out } } } { "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Signal_Freq_Out" } } } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 20 -1 0 } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Signal_Freq_Out } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Signal_Freq_Out } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "Signal_RUN_DIS a permanently enabled " "Info: Pin Signal_RUN_DIS has a permanently enabled output enable" {  } { { "d:/quartus ii 7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/quartus ii 7.2/quartus/bin/pin_planner.ppl" { Signal_RUN_DIS } } } { "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Signal_RUN_DIS" } } } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 21 -1 0 } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Signal_RUN_DIS } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Signal_RUN_DIS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/Administrator/桌面/SIN/SIN.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/Administrator/桌面/SIN/SIN.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "168 " "Info: Allocated 168 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 16:51:13 2008 " "Info: Processing ended: Mon Oct 27 16:51:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}