sin.tan.qmsg

使用VHDL语言和CPLD芯片生成39KHz的信号

{ "Info" "ITDB_TH_RESULT" "Set_Freq_OLD_IN\[4\] Set_Freq_IN\[4\] CLK -1.279 ns register " "Info: th for register \"Set_Freq_OLD_IN\[4\]\" (data pin = \"Set_Freq_IN\[4\]\", clock pin = \"CLK\") is -1.279 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.458 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns Set_Freq_OLD_IN\[4\] 2 REG LC_X3_Y4_N0 1 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X3_Y4_N0; Fanout = 1; REG Node = 'Set_Freq_OLD_IN\[4\]'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLK Set_Freq_OLD_IN[4] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Set_Freq_OLD_IN[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Set_Freq_OLD_IN[4] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.958 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Set_Freq_IN\[4\] 1 PIN PIN_98 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_98; Fanout = 7; PIN Node = 'Set_Freq_IN\[4\]'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Set_Freq_IN[4] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.546 ns) + CELL(0.280 ns) 4.958 ns Set_Freq_OLD_IN\[4\] 2 REG LC_X3_Y4_N0 1 " "Info: 2: + IC(3.546 ns) + CELL(0.280 ns) = 4.958 ns; Loc. = LC_X3_Y4_N0; Fanout = 1; REG Node = 'Set_Freq_OLD_IN\[4\]'" {  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.826 ns" { Set_Freq_IN[4] Set_Freq_OLD_IN[4] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 28.48 % ) " "Info: Total cell delay = 1.412 ns ( 28.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.546 ns ( 71.52 % ) " "Info: Total interconnect delay = 3.546 ns ( 71.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.958 ns" { Set_Freq_IN[4] Set_Freq_OLD_IN[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "4.958 ns" { Set_Freq_IN[4] {} Set_Freq_IN[4]~combout {} Set_Freq_OLD_IN[4] {} } { 0.000ns 0.000ns 3.546ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Set_Freq_OLD_IN[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Set_Freq_OLD_IN[4] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.958 ns" { Set_Freq_IN[4] Set_Freq_OLD_IN[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "4.958 ns" { Set_Freq_IN[4] {} Set_Freq_IN[4]~combout {} Set_Freq_OLD_IN[4] {} } { 0.000ns 0.000ns 3.546ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 16:51:47 2008 " "Info: Processing ended: Mon Oct 27 16:51:47 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}