📄 sin.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } { "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Signal_Freq_Out~reg0 " "Info: Detected ripple clock \"Signal_Freq_Out~reg0\" as buffer" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 0 0 } } { "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Signal_Freq_Out~reg0" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register Count_Freq\[0\] register Count_Freq\[7\] 117.81 MHz 8.488 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 117.81 MHz between source register \"Count_Freq\[0\]\" and destination register \"Count_Freq\[7\]\" (period= 8.488 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.779 ns + Longest register register " "Info: + Longest register to register delay is 7.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Count_Freq\[0\] 1 REG LC_X4_Y3_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N0; Fanout = 4; REG Node = 'Count_Freq\[0\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Count_Freq[0] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(0.914 ns) 2.209 ns LessThan1~459 2 COMB LC_X3_Y3_N4 1 " "Info: 2: + IC(1.295 ns) + CELL(0.914 ns) = 2.209 ns; Loc. = LC_X3_Y3_N4; Fanout = 1; COMB Node = 'LessThan1~459'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.209 ns" { Count_Freq[0] LessThan1~459 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.200 ns) 2.943 ns LessThan1~460 3 COMB LC_X3_Y3_N5 1 " "Info: 3: + IC(0.534 ns) + CELL(0.200 ns) = 2.943 ns; Loc. = LC_X3_Y3_N5; Fanout = 1; COMB Node = 'LessThan1~460'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { LessThan1~459 LessThan1~460 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.448 ns LessThan1~461 4 COMB LC_X3_Y3_N6 1 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 3.448 ns; Loc. = LC_X3_Y3_N6; Fanout = 1; COMB Node = 'LessThan1~461'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan1~460 LessThan1~461 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.953 ns LessThan1~462 5 COMB LC_X3_Y3_N7 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 3.953 ns; Loc. = LC_X3_Y3_N7; Fanout = 1; COMB Node = 'LessThan1~462'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan1~461 LessThan1~462 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.458 ns LessThan1~463 6 COMB LC_X3_Y3_N8 1 " "Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 4.458 ns; Loc. = LC_X3_Y3_N8; Fanout = 1; COMB Node = 'LessThan1~463'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan1~462 LessThan1~463 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.963 ns LessThan1~464 7 COMB LC_X3_Y3_N9 11 " "Info: 7: + IC(0.305 ns) + CELL(0.200 ns) = 4.963 ns; Loc. = LC_X3_Y3_N9; Fanout = 11; COMB Node = 'LessThan1~464'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan1~463 LessThan1~464 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.056 ns) + CELL(1.760 ns) 7.779 ns Count_Freq\[7\] 8 REG LC_X4_Y3_N7 4 " "Info: 8: + IC(1.056 ns) + CELL(1.760 ns) = 7.779 ns; Loc. = LC_X4_Y3_N7; Fanout = 4; REG Node = 'Count_Freq\[7\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { LessThan1~464 Count_Freq[7] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.674 ns ( 47.23 % ) " "Info: Total cell delay = 3.674 ns ( 47.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.105 ns ( 52.77 % ) " "Info: Total interconnect delay = 4.105 ns ( 52.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.779 ns" { Count_Freq[0] LessThan1~459 LessThan1~460 LessThan1~461 LessThan1~462 LessThan1~463 LessThan1~464 Count_Freq[7] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "7.779 ns" { Count_Freq[0] {} LessThan1~459 {} LessThan1~460 {} LessThan1~461 {} LessThan1~462 {} LessThan1~463 {} LessThan1~464 {} Count_Freq[7] {} } { 0.000ns 1.295ns 0.534ns 0.305ns 0.305ns 0.305ns 0.305ns 1.056ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.760ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.458 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns Count_Freq\[7\] 2 REG LC_X4_Y3_N7 4 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X4_Y3_N7; Fanout = 4; REG Node = 'Count_Freq\[7\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLK Count_Freq[7] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[7] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[7] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.458 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns Count_Freq\[0\] 2 REG LC_X4_Y3_N0 4 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X4_Y3_N0; Fanout = 4; REG Node = 'Count_Freq\[0\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLK Count_Freq[0] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[0] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[7] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[7] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[0] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.779 ns" { Count_Freq[0] LessThan1~459 LessThan1~460 LessThan1~461 LessThan1~462 LessThan1~463 LessThan1~464 Count_Freq[7] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "7.779 ns" { Count_Freq[0] {} LessThan1~459 {} LessThan1~460 {} LessThan1~461 {} LessThan1~462 {} LessThan1~463 {} LessThan1~464 {} Count_Freq[7] {} } { 0.000ns 1.295ns 0.534ns 0.305ns 0.305ns 0.305ns 0.305ns 1.056ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.760ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[7] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[7] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[0] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Count_Set_Freq\[8\] Set_Freq_IN\[4\] CLK 5.872 ns register " "Info: tsu for register \"Count_Set_Freq\[8\]\" (data pin = \"Set_Freq_IN\[4\]\", clock pin = \"CLK\") is 5.872 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.997 ns + Longest pin register " "Info: + Longest pin to register delay is 8.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Set_Freq_IN\[4\] 1 PIN PIN_98 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_98; Fanout = 7; PIN Node = 'Set_Freq_IN\[4\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Set_Freq_IN[4] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.813 ns) + CELL(0.740 ns) 4.685 ns Equal0~33 2 COMB LC_X3_Y4_N0 1 " "Info: 2: + IC(2.813 ns) + CELL(0.740 ns) = 4.685 ns; Loc. = LC_X3_Y4_N0; Fanout = 1; COMB Node = 'Equal0~33'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.553 ns" { Set_Freq_IN[4] Equal0~33 } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.740 ns) 6.154 ns Equal0~34 3 COMB LC_X3_Y4_N3 16 " "Info: 3: + IC(0.729 ns) + CELL(0.740 ns) = 6.154 ns; Loc. = LC_X3_Y4_N3; Fanout = 16; COMB Node = 'Equal0~34'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.469 ns" { Equal0~33 Equal0~34 } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.083 ns) + CELL(1.760 ns) 8.997 ns Count_Set_Freq\[8\] 4 REG LC_X4_Y4_N8 4 " "Info: 4: + IC(1.083 ns) + CELL(1.760 ns) = 8.997 ns; Loc. = LC_X4_Y4_N8; Fanout = 4; REG Node = 'Count_Set_Freq\[8\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { Equal0~34 Count_Set_Freq[8] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.372 ns ( 48.59 % ) " "Info: Total cell delay = 4.372 ns ( 48.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.625 ns ( 51.41 % ) " "Info: Total interconnect delay = 4.625 ns ( 51.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "8.997 ns" { Set_Freq_IN[4] Equal0~33 Equal0~34 Count_Set_Freq[8] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "8.997 ns" { Set_Freq_IN[4] {} Set_Freq_IN[4]~combout {} Equal0~33 {} Equal0~34 {} Count_Set_Freq[8] {} } { 0.000ns 0.000ns 2.813ns 0.729ns 1.083ns } { 0.000ns 1.132ns 0.740ns 0.740ns 1.760ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.458 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns Count_Set_Freq\[8\] 2 REG LC_X4_Y4_N8 4 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X4_Y4_N8; Fanout = 4; REG Node = 'Count_Set_Freq\[8\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLK Count_Set_Freq[8] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Set_Freq[8] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Set_Freq[8] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "8.997 ns" { Set_Freq_IN[4] Equal0~33 Equal0~34 Count_Set_Freq[8] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "8.997 ns" { Set_Freq_IN[4] {} Set_Freq_IN[4]~combout {} Equal0~33 {} Equal0~34 {} Count_Set_Freq[8] {} } { 0.000ns 0.000ns 2.813ns 0.729ns 1.083ns } { 0.000ns 1.132ns 0.740ns 0.740ns 1.760ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Set_Freq[8] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Set_Freq[8] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Signal_RUN_DIS Signal_RUN_DIS~reg0 11.024 ns register " "Info: tco from clock \"CLK\" to destination pin \"Signal_RUN_DIS\" through register \"Signal_RUN_DIS~reg0\" is 11.024 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.524 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.524 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns Signal_Freq_Out~reg0 2 REG LC_X2_Y3_N2 17 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X2_Y3_N2; Fanout = 17; REG Node = 'Signal_Freq_Out~reg0'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { CLK Signal_Freq_Out~reg0 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.772 ns) + CELL(0.918 ns) 7.524 ns Signal_RUN_DIS~reg0 3 REG LC_X2_Y1_N8 2 " "Info: 3: + IC(2.772 ns) + CELL(0.918 ns) = 7.524 ns; Loc. = LC_X2_Y1_N8; Fanout = 2; REG Node = 'Signal_RUN_DIS~reg0'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.690 ns" { Signal_Freq_Out~reg0 Signal_RUN_DIS~reg0 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 82 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 44.86 % ) " "Info: Total cell delay = 3.375 ns ( 44.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.149 ns ( 55.14 % ) " "Info: Total interconnect delay = 4.149 ns ( 55.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.524 ns" { CLK Signal_Freq_Out~reg0 Signal_RUN_DIS~reg0 } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "7.524 ns" { CLK {} CLK~combout {} Signal_Freq_Out~reg0 {} Signal_RUN_DIS~reg0 {} } { 0.000ns 0.000ns 1.377ns 2.772ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 82 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.124 ns + Longest register pin " "Info: + Longest register to pin delay is 3.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Signal_RUN_DIS~reg0 1 REG LC_X2_Y1_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N8; Fanout = 2; REG Node = 'Signal_RUN_DIS~reg0'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Signal_RUN_DIS~reg0 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 82 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.802 ns) + CELL(2.322 ns) 3.124 ns Signal_RUN_DIS 2 PIN PIN_26 0 " "Info: 2: + IC(0.802 ns) + CELL(2.322 ns) = 3.124 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'Signal_RUN_DIS'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.124 ns" { Signal_RUN_DIS~reg0 Signal_RUN_DIS } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 74.33 % ) " "Info: Total cell delay = 2.322 ns ( 74.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.802 ns ( 25.67 % ) " "Info: Total interconnect delay = 0.802 ns ( 25.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.124 ns" { Signal_RUN_DIS~reg0 Signal_RUN_DIS } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.124 ns" { Signal_RUN_DIS~reg0 {} Signal_RUN_DIS {} } { 0.000ns 0.802ns } { 0.000ns 2.322ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.524 ns" { CLK Signal_Freq_Out~reg0 Signal_RUN_DIS~reg0 } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "7.524 ns" { CLK {} CLK~combout {} Signal_Freq_Out~reg0 {} Signal_RUN_DIS~reg0 {} } { 0.000ns 0.000ns 1.377ns 2.772ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.124 ns" { Signal_RUN_DIS~reg0 Signal_RUN_DIS } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.124 ns" { Signal_RUN_DIS~reg0 {} Signal_RUN_DIS {} } { 0.000ns 0.802ns } { 0.000ns 2.322ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
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