prev_cmp_sin.map.qmsg

使用VHDL语言和CPLD芯片生成39KHz的信号

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 27 16:49:35 2008 " "Info: Processing started: Mon Oct 27 16:49:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SIN -c SIN " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SIN -c SIN" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SIN.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SIN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SIN-using_std_logic " "Info: Found design unit 1: SIN-using_std_logic" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 SIN " "Info: Found entity 1: SIN" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SIN " "Info: Elaborating entity \"SIN\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "VAL_Freq_Set\[8\] data_in GND " "Warning (14130): Reduced register \"VAL_Freq_Set\[8\]\" with stuck data_in port to stuck value GND" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "VAL_Freq_Set\[1\] VAL_Freq_Set\[0\] " "Info: Duplicate register \"VAL_Freq_Set\[1\]\" merged to single register \"VAL_Freq_Set\[0\]\"" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "VAL_Freq_Set\[2\] VAL_Freq_Set\[0\] " "Info: Duplicate register \"VAL_Freq_Set\[2\]\" merged to single register \"VAL_Freq_Set\[0\]\"" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "VAL_Freq_Set\[7\] VAL_Freq_Set\[3\] " "Info: Duplicate register \"VAL_Freq_Set\[7\]\" merged to single register \"VAL_Freq_Set\[3\]\"" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "Signal_Freq_Out~1 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus Signal_Freq_Out~1 that it feeds" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 20 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "Signal_RUN_DIS~1 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus Signal_RUN_DIS~1 that it feeds" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 21 -1 0 } }  } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_HDR" "" "Info: One or more bidirs are fed by always enabled tri-state buffers" { { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "Signal_Freq_Out " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"Signal_Freq_Out\" is moved to its source" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 20 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "Signal_RUN_DIS " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"Signal_RUN_DIS\" is moved to its source" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 21 -1 0 } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0 "" 0}  } {  } 0 0 "One or more bidirs are fed by always enabled tri-state buffers" 0 0 "" 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "Signal_Freq_Out~10 " "Warning: Node \"Signal_Freq_Out~10\"" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 20 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "Signal_RUN_DIS~10 " "Warning: Node \"Signal_RUN_DIS~10\"" {  } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Info: Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "0 " "Info: Implemented 0 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "2 " "Info: Implemented 2 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "64 " "Info: Implemented 64 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 16:49:44 2008 " "Info: Processing ended: Mon Oct 27 16:49:44 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}