📄 prev_cmp_sin.qmsg
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{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "127 " "Info: Allocated 127 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 16:49:58 2008 " "Info: Processing ended: Mon Oct 27 16:49:58 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 27 16:50:00 2008 " "Info: Processing started: Mon Oct 27 16:50:00 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off SIN -c SIN " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SIN -c SIN" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } { "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Signal_Freq_Out~reg0 " "Info: Detected ripple clock \"Signal_Freq_Out~reg0\" as buffer" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 0 0 } } { "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Signal_Freq_Out~reg0" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register VAL_Freq_Set\[3\] register Count_Freq\[4\] 110.41 MHz 9.057 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 110.41 MHz between source register \"VAL_Freq_Set\[3\]\" and destination register \"Count_Freq\[4\]\" (period= 9.057 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.348 ns + Longest register register " "Info: + Longest register to register delay is 8.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VAL_Freq_Set\[3\] 1 REG LC_X2_Y2_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y2_N7; Fanout = 3; REG Node = 'VAL_Freq_Set\[3\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { VAL_Freq_Set[3] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.133 ns) + CELL(0.740 ns) 2.873 ns LessThan1~542 2 COMB LC_X2_Y3_N0 1 " "Info: 2: + IC(2.133 ns) + CELL(0.740 ns) = 2.873 ns; Loc. = LC_X2_Y3_N0; Fanout = 1; COMB Node = 'LessThan1~542'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { VAL_Freq_Set[3] LessThan1~542 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.511 ns) 4.167 ns LessThan1~543 3 COMB LC_X2_Y3_N7 2 " "Info: 3: + IC(0.783 ns) + CELL(0.511 ns) = 4.167 ns; Loc. = LC_X2_Y3_N7; Fanout = 2; COMB Node = 'LessThan1~543'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.294 ns" { LessThan1~542 LessThan1~543 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.785 ns) + CELL(0.511 ns) 5.463 ns LessThan1~545 4 COMB LC_X2_Y3_N5 10 " "Info: 4: + IC(0.785 ns) + CELL(0.511 ns) = 5.463 ns; Loc. = LC_X2_Y3_N5; Fanout = 10; COMB Node = 'LessThan1~545'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { LessThan1~543 LessThan1~545 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.125 ns) + CELL(1.760 ns) 8.348 ns Count_Freq\[4\] 5 REG LC_X3_Y3_N4 3 " "Info: 5: + IC(1.125 ns) + CELL(1.760 ns) = 8.348 ns; Loc. = LC_X3_Y3_N4; Fanout = 3; REG Node = 'Count_Freq\[4\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.885 ns" { LessThan1~545 Count_Freq[4] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.522 ns ( 42.19 % ) " "Info: Total cell delay = 3.522 ns ( 42.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.826 ns ( 57.81 % ) " "Info: Total interconnect delay = 4.826 ns ( 57.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "8.348 ns" { VAL_Freq_Set[3] LessThan1~542 LessThan1~543 LessThan1~545 Count_Freq[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "8.348 ns" { VAL_Freq_Set[3] {} LessThan1~542 {} LessThan1~543 {} LessThan1~545 {} Count_Freq[4] {} } { 0.000ns 2.133ns 0.783ns 0.785ns 1.125ns } { 0.000ns 0.740ns 0.511ns 0.511ns 1.760ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.458 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns Count_Freq\[4\] 2 REG LC_X3_Y3_N4 3 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X3_Y3_N4; Fanout = 3; REG Node = 'Count_Freq\[4\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLK Count_Freq[4] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[4] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.458 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns VAL_Freq_Set\[3\] 2 REG LC_X2_Y2_N7 3 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X2_Y2_N7; Fanout = 3; REG Node = 'VAL_Freq_Set\[3\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLK VAL_Freq_Set[3] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK VAL_Freq_Set[3] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} VAL_Freq_Set[3] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[4] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK VAL_Freq_Set[3] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} VAL_Freq_Set[3] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "8.348 ns" { VAL_Freq_Set[3] LessThan1~542 LessThan1~543 LessThan1~545 Count_Freq[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "8.348 ns" { VAL_Freq_Set[3] {} LessThan1~542 {} LessThan1~543 {} LessThan1~545 {} Count_Freq[4] {} } { 0.000ns 2.133ns 0.783ns 0.785ns 1.125ns } { 0.000ns 0.740ns 0.511ns 0.511ns 1.760ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Freq[4] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Freq[4] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK VAL_Freq_Set[3] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} VAL_Freq_Set[3] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Count_Set_Freq\[9\] Set_Freq_IN\[4\] CLK 5.882 ns register " "Info: tsu for register \"Count_Set_Freq\[9\]\" (data pin = \"Set_Freq_IN\[4\]\", clock pin = \"CLK\") is 5.882 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.007 ns + Longest pin register " "Info: + Longest pin to register delay is 9.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Set_Freq_IN\[4\] 1 PIN PIN_98 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_98; Fanout = 7; PIN Node = 'Set_Freq_IN\[4\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Set_Freq_IN[4] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.631 ns) + CELL(0.914 ns) 4.677 ns Equal0~33 2 COMB LC_X2_Y2_N1 1 " "Info: 2: + IC(2.631 ns) + CELL(0.914 ns) = 4.677 ns; Loc. = LC_X2_Y2_N1; Fanout = 1; COMB Node = 'Equal0~33'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.545 ns" { Set_Freq_IN[4] Equal0~33 } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.718 ns) + CELL(0.740 ns) 6.135 ns Equal0~34 3 COMB LC_X2_Y2_N3 16 " "Info: 3: + IC(0.718 ns) + CELL(0.740 ns) = 6.135 ns; Loc. = LC_X2_Y2_N3; Fanout = 16; COMB Node = 'Equal0~34'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.458 ns" { Equal0~33 Equal0~34 } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(1.760 ns) 9.007 ns Count_Set_Freq\[9\] 4 REG LC_X3_Y2_N9 2 " "Info: 4: + IC(1.112 ns) + CELL(1.760 ns) = 9.007 ns; Loc. = LC_X3_Y2_N9; Fanout = 2; REG Node = 'Count_Set_Freq\[9\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Equal0~34 Count_Set_Freq[9] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.546 ns ( 50.47 % ) " "Info: Total cell delay = 4.546 ns ( 50.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.461 ns ( 49.53 % ) " "Info: Total interconnect delay = 4.461 ns ( 49.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "9.007 ns" { Set_Freq_IN[4] Equal0~33 Equal0~34 Count_Set_Freq[9] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "9.007 ns" { Set_Freq_IN[4] {} Set_Freq_IN[4]~combout {} Equal0~33 {} Equal0~34 {} Count_Set_Freq[9] {} } { 0.000ns 0.000ns 2.631ns 0.718ns 1.112ns } { 0.000ns 1.132ns 0.914ns 0.740ns 1.760ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.458 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns Count_Set_Freq\[9\] 2 REG LC_X3_Y2_N9 2 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X3_Y2_N9; Fanout = 2; REG Node = 'Count_Set_Freq\[9\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLK Count_Set_Freq[9] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Set_Freq[9] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Set_Freq[9] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "9.007 ns" { Set_Freq_IN[4] Equal0~33 Equal0~34 Count_Set_Freq[9] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "9.007 ns" { Set_Freq_IN[4] {} Set_Freq_IN[4]~combout {} Equal0~33 {} Equal0~34 {} Count_Set_Freq[9] {} } { 0.000ns 0.000ns 2.631ns 0.718ns 1.112ns } { 0.000ns 1.132ns 0.914ns 0.740ns 1.760ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK Count_Set_Freq[9] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} Count_Set_Freq[9] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Signal_RUN_DIS Signal_RUN_DIS~reg0 12.099 ns register " "Info: tco from clock \"CLK\" to destination pin \"Signal_RUN_DIS\" through register \"Signal_RUN_DIS~reg0\" is 12.099 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.521 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.521 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns Signal_Freq_Out~reg0 2 REG LC_X2_Y3_N9 17 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X2_Y3_N9; Fanout = 17; REG Node = 'Signal_Freq_Out~reg0'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { CLK Signal_Freq_Out~reg0 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 70 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.769 ns) + CELL(0.918 ns) 7.521 ns Signal_RUN_DIS~reg0 3 REG LC_X2_Y1_N0 2 " "Info: 3: + IC(2.769 ns) + CELL(0.918 ns) = 7.521 ns; Loc. = LC_X2_Y1_N0; Fanout = 2; REG Node = 'Signal_RUN_DIS~reg0'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.687 ns" { Signal_Freq_Out~reg0 Signal_RUN_DIS~reg0 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 82 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 44.87 % ) " "Info: Total cell delay = 3.375 ns ( 44.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.146 ns ( 55.13 % ) " "Info: Total interconnect delay = 4.146 ns ( 55.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.521 ns" { CLK Signal_Freq_Out~reg0 Signal_RUN_DIS~reg0 } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "7.521 ns" { CLK {} CLK~combout {} Signal_Freq_Out~reg0 {} Signal_RUN_DIS~reg0 {} } { 0.000ns 0.000ns 1.377ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 82 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.202 ns + Longest register pin " "Info: + Longest register to pin delay is 4.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Signal_RUN_DIS~reg0 1 REG LC_X2_Y1_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N0; Fanout = 2; REG Node = 'Signal_RUN_DIS~reg0'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Signal_RUN_DIS~reg0 } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 82 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(2.322 ns) 4.202 ns Signal_RUN_DIS 2 PIN PIN_26 0 " "Info: 2: + IC(1.880 ns) + CELL(2.322 ns) = 4.202 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'Signal_RUN_DIS'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { Signal_RUN_DIS~reg0 Signal_RUN_DIS } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 55.26 % ) " "Info: Total cell delay = 2.322 ns ( 55.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.880 ns ( 44.74 % ) " "Info: Total interconnect delay = 1.880 ns ( 44.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { Signal_RUN_DIS~reg0 Signal_RUN_DIS } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "4.202 ns" { Signal_RUN_DIS~reg0 {} Signal_RUN_DIS {} } { 0.000ns 1.880ns } { 0.000ns 2.322ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.521 ns" { CLK Signal_Freq_Out~reg0 Signal_RUN_DIS~reg0 } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "7.521 ns" { CLK {} CLK~combout {} Signal_Freq_Out~reg0 {} Signal_RUN_DIS~reg0 {} } { 0.000ns 0.000ns 1.377ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { Signal_RUN_DIS~reg0 Signal_RUN_DIS } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "4.202 ns" { Signal_RUN_DIS~reg0 {} Signal_RUN_DIS {} } { 0.000ns 1.880ns } { 0.000ns 2.322ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "VAL_Freq_Set\[5\] Set_Freq_IN\[2\] CLK -1.588 ns register " "Info: th for register \"VAL_Freq_Set\[5\]\" (data pin = \"Set_Freq_IN\[2\]\", clock pin = \"CLK\") is -1.588 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.458 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_62 30 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 30; CLK Node = 'CLK'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns VAL_Freq_Set\[5\] 2 REG LC_X2_Y2_N6 2 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X2_Y2_N6; Fanout = 2; REG Node = 'VAL_Freq_Set\[5\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLK VAL_Freq_Set[5] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK VAL_Freq_Set[5] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} VAL_Freq_Set[5] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.267 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Set_Freq_IN\[2\] 1 PIN PIN_100 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_100; Fanout = 7; PIN Node = 'Set_Freq_IN\[2\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Set_Freq_IN[2] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.074 ns) + CELL(1.061 ns) 5.267 ns VAL_Freq_Set\[5\] 2 REG LC_X2_Y2_N6 2 " "Info: 2: + IC(3.074 ns) + CELL(1.061 ns) = 5.267 ns; Loc. = LC_X2_Y2_N6; Fanout = 2; REG Node = 'VAL_Freq_Set\[5\]'" { } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.135 ns" { Set_Freq_IN[2] VAL_Freq_Set[5] } "NODE_NAME" } } { "SIN.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 41.64 % ) " "Info: Total cell delay = 2.193 ns ( 41.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.074 ns ( 58.36 % ) " "Info: Total interconnect delay = 3.074 ns ( 58.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.267 ns" { Set_Freq_IN[2] VAL_Freq_Set[5] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "5.267 ns" { Set_Freq_IN[2] {} Set_Freq_IN[2]~combout {} VAL_Freq_Set[5] {} } { 0.000ns 0.000ns 3.074ns } { 0.000ns 1.132ns 1.061ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLK VAL_Freq_Set[5] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLK {} CLK~combout {} VAL_Freq_Set[5] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.267 ns" { Set_Freq_IN[2] VAL_Freq_Set[5] } "NODE_NAME" } } { "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "5.267 ns" { Set_Freq_IN[2] {} Set_Freq_IN[2]~combout {} VAL_Freq_Set[5] {} } { 0.000ns 0.000ns 3.074ns } { 0.000ns 1.132ns 1.061ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 27 16:50:04 2008 " "Info: Processing ended: Mon Oct 27 16:50:04 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Info: Quartus II Full Compilation was successful. 0 errors, 11 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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