sin.flow.rpt

使用VHDL语言和CPLD芯片生成39KHz的信号

Flow report for SIN
Mon Oct 27 16:51:46 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; Flow Summary                                                        ;
+--------------------------+------------------------------------------+
; Flow Status              ; Successful - Mon Oct 27 16:51:46 2008    ;
; Quartus II Version       ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name            ; SIN                                      ;
; Top-level Entity Name    ; SIN                                      ;
; Family                   ; MAX II                                   ;
; Device                   ; EPM240T100I5                             ;
; Timing Models            ; Final                                    ;
; Met timing requirements  ; Yes                                      ;
; Total logic elements     ; 58 / 240 ( 24 % )                        ;
; Total pins               ; 7 / 80 ( 9 % )                           ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 0                                        ;
; DSP block 9-bit elements ; 0                                        ;
; Total PLLs               ; 0                                        ;
; Total DLLs               ; 0                                        ;
; UFM blocks               ; 0 / 1 ( 0 % )                            ;
+--------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 10/27/2008 16:50:56 ;
; Main task         ; Compilation         ;
; Revision Name     ; SIN                 ;
+-------------------+---------------------+


+--------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                 ;
+-------------------------+--------------+------------------------------+-------------+------------+
; Assignment Name         ; Value        ; Default Value                ; Entity Name ; Section Id ;
+-------------------------+--------------+------------------------------+-------------+------------+
; FITTER_EFFORT           ; Standard Fit ; Auto Fit                     ; --          ; --         ;
; INCREMENTAL_COMPILATION ; Off          ; FULL_INCREMENTAL_COMPILATION ; --          ; --         ;
+-------------------------+--------------+------------------------------+-------------+------------+


+------------------------------------------------------------------+
; Flow Elapsed Time                                                ;
+-------------------------+--------------+-------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ;
+-------------------------+--------------+-------------------------+
; Analysis & Synthesis    ; 00:00:10     ; 1.0                     ;
; Fitter                  ; 00:00:05     ; 1.0                     ;
; Assembler               ; 00:00:26     ; 1.0                     ;
; Classic Timing Analyzer ; 00:00:02     ; 1.0                     ;
; Total                   ; 00:00:43     ; --                      ;
+-------------------------+--------------+-------------------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off SIN -c SIN
quartus_fit --read_settings_files=off --write_settings_files=off SIN -c SIN
quartus_asm --read_settings_files=off --write_settings_files=off SIN -c SIN
quartus_tan --read_settings_files=off --write_settings_files=off SIN -c SIN