📄 sin.fit.rpt
字号:
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 1 ;
+---------------------------------------------+-----------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+--------------------------------------------------------------------------------+-------------+
; Name ; Value ;
+--------------------------------------------------------------------------------+-------------+
; Mid Wire Use - Fit Attempt 1 ; 10 ;
; Mid Slack - Fit Attempt 1 ; -10593 ;
; Internal Atom Count - Fit Attempt 1 ; 58 ;
; LE/ALM Count - Fit Attempt 1 ; 58 ;
; LAB Count - Fit Attempt 1 ; 7 ;
; Outputs per Lab - Fit Attempt 1 ; 4.286 ;
; Inputs per LAB - Fit Attempt 1 ; 5.143 ;
; Global Inputs per LAB - Fit Attempt 1 ; 0.857 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:7 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:6;2:1 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2;1:4;2:1 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:2;1:4;2:1 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 0:2;1:4;2:1 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 0:2;1:4;2:1 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:3;1:4 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:7 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:6;1:1 ;
; LAB Constraint 'global control signals' - Fit Attempt 1 ; 0:1;1:6 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:5;2:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:7 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 0:1;1:6 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:2;1:5 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 1:7 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:5;1:2 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:7 ;
; LEs in Chains - Fit Attempt 1 ; 34 ;
; LEs in Long Chains - Fit Attempt 1 ; 14 ;
; LABs with Chains - Fit Attempt 1 ; 4 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+--------------------------------------------------------------------------------+-------------+
+----------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1 ; 1 ;
; Early Slack - Fit Attempt 1 ; -13274 ;
; Mid Wire Use - Fit Attempt 1 ; 3 ;
; Mid Slack - Fit Attempt 1 ; -10309 ;
; Late Wire Use - Fit Attempt 1 ; 4 ;
; Late Slack - Fit Attempt 1 ; -10309 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Time - Fit Attempt 1 ; 2 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.250 ;
+-------------------------------------+--------+
+----------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1 ; -10498 ;
; Early Wire Use - Fit Attempt 1 ; 3 ;
; Peak Regional Wire - Fit Attempt 1 ; 2 ;
; Mid Slack - Fit Attempt 1 ; -10504 ;
; Late Slack - Fit Attempt 1 ; -10504 ;
; Late Wire Use - Fit Attempt 1 ; 4 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.093 ;
+-------------------------------------+--------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Mon Oct 27 16:51:07 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SIN -c SIN
Info: Selected device EPM240T100I5 for design "SIN"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '100'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '-40'.
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240T100C5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN 62
Info: Automatically promoted some destinations of signal "Signal_Freq_Out~reg0" to use Global clock
Info: Destination "Signal_Freq_Out" may be non-global or may not use global clock
Info: Destination "Signal_Freq_Out~reg0" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to register delay of 10.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 4; REG Node = 'Count_Freq[0]'
Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~459'
Info: 3: + IC(0.669 ns) + CELL(0.511 ns) = 2.937 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~460'
Info: 4: + IC(0.669 ns) + CELL(0.511 ns) = 4.117 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~461'
Info: 5: + IC(0.669 ns) + CELL(0.511 ns) = 5.297 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~462'
Info: 6: + IC(0.669 ns) + CELL(0.511 ns) = 6.477 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan1~463'
Info: 7: + IC(0.440 ns) + CELL(0.740 ns) = 7.657 ns; Loc. = LAB_X3_Y3; Fanout = 11; COMB Node = 'LessThan1~464'
Info: 8: + IC(1.183 ns) + CELL(1.760 ns) = 10.600 ns; Loc. = LAB_X4_Y3; Fanout = 4; REG Node = 'Count_Freq[7]'
Info: Total cell delay = 4.744 ns ( 44.75 % )
Info: Total interconnect delay = 5.856 ns ( 55.25 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources
Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Warning: Following 2 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
Info: Pin Signal_Freq_Out has a permanently enabled output enable
Info: Pin Signal_RUN_DIS has a permanently enabled output enable
Info: Generated suppressed messages file C:/Documents and Settings/Administrator/桌面/SIN/SIN.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Allocated 168 megabytes of memory during processing
Info: Processing ended: Mon Oct 27 16:51:13 2008
Info: Elapsed time: 00:00:06
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Documents and Settings/Administrator/桌面/SIN/SIN.fit.smsg.
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -