sin.tan.rpt
来自「使用VHDL语言和CPLD芯片生成39KHz的信号」· RPT 代码 · 共 371 行 · 第 1/5 页
RPT
371 行
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-----------------------------------------+-----------------------------------------------------+-------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[7] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[8] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[9] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[6] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[4] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[5] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[3] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[2] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[1] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 117.81 MHz ( period = 8.488 ns ) ; Count_Freq[0] ; Count_Freq[0] ; CLK ; CLK ; None ; None ; 7.779 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[7] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[8] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[9] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[6] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[4] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[5] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[3] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[2] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[1] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 119.96 MHz ( period = 8.336 ns ) ; Count_Freq[2] ; Count_Freq[0] ; CLK ; CLK ; None ; None ; 7.627 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[7] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[8] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[9] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[6] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[4] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[5] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[3] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[2] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[1] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.44 MHz ( period = 8.167 ns ) ; VAL_Freq_Set[4] ; Count_Freq[0] ; CLK ; CLK ; None ; None ; 7.458 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[7] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[8] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[9] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[6] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[4] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[5] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[3] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[2] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[1] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 122.87 MHz ( period = 8.139 ns ) ; Count_Freq[3] ; Count_Freq[0] ; CLK ; CLK ; None ; None ; 7.430 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[7] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[8] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[9] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[6] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[4] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[5] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[3] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[2] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[1] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 126.41 MHz ( period = 7.911 ns ) ; VAL_Freq_Set[5] ; Count_Freq[0] ; CLK ; CLK ; None ; None ; 7.202 ns ;
; N/A ; 127.99 MHz ( period = 7.813 ns ) ; Count_Set_Freq[5] ; VAL_Freq_Set[4] ; CLK ; CLK ; None ; None ; 7.104 ns ;
; N/A ; 127.99 MHz ( period = 7.813 ns ) ; Count_Set_Freq[5] ; VAL_Freq_Set[7] ; CLK ; CLK ; None ; None ; 7.104 ns ;
; N/A ; 127.99 MHz ( period = 7.813 ns ) ; Count_Set_Freq[5] ; VAL_Freq_Set[6] ; CLK ; CLK ; None ; None ; 7.104 ns ;
; N/A ; 127.99 MHz ( period = 7.813 ns ) ; Count_Set_Freq[5] ; VAL_Freq_Set[5] ; CLK ; CLK ; None ; None ; 7.104 ns ;
; N/A ; 128.22 MHz ( period = 7.799 ns ) ; Count_Freq[1] ; Count_Freq[7] ; CLK ; CLK ; None ; None ; 7.090 ns ;
; N/A ; 128.22 MHz ( period = 7.799 ns ) ; Count_Freq[1] ; Count_Freq[8] ; CLK ; CLK ; None ; None ; 7.090 ns ;
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