sin.tan.summary

使用VHDL语言和CPLD芯片生成39KHz的信号

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.872 ns
From           : Set_Freq_IN[4]
To             : Count_Set_Freq[6]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.024 ns
From           : Signal_RUN_DIS~reg0
To             : Signal_RUN_DIS
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.279 ns
From           : Set_Freq_IN[4]
To             : Set_Freq_OLD_IN[4]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 117.81 MHz ( period = 8.488 ns )
From           : Count_Freq[0]
To             : Count_Freq[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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