sin.map.rpt

使用VHDL语言和CPLD芯片生成39KHz的信号

; SIN.vhd                          ; yes             ; User VHDL File  ; C:/Documents and Settings/Administrator/桌面/SIN/SIN.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 61    ;
;     -- Combinational with no register       ; 16    ;
;     -- Register only                        ; 4     ;
;     -- Combinational with a register        ; 41    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 16    ;
;     -- 3 input functions                    ; 4     ;
;     -- 2 input functions                    ; 35    ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 30    ;
;     -- arithmetic mode                      ; 31    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 34    ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 45    ;
; Total logic cells in carry chains           ; 34    ;
; I/O pins                                    ; 7     ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 30    ;
; Total fan-out                               ; 241   ;
; Average fan-out                             ; 3.54  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |SIN                       ; 61 (61)     ; 45           ; 0           ; 0            ; 0       ; 0         ; 0         ; 7    ; 0            ; 16 (16)      ; 4 (4)             ; 41 (41)          ; 34 (34)         ; 0 (0)      ; |SIN                ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------+
; Registers Removed During Synthesis                                  ;
+---------------------------------------+-----------------------------+
; Register name                         ; Reason for Removal          ;
+---------------------------------------+-----------------------------+
; VAL_Freq_Set[1..3]                    ; Merged with VAL_Freq_Set[0] ;
; VAL_Freq_Set[8]                       ; Merged with VAL_Freq_Set[4] ;
; Total Number of Removed Registers = 4 ;                             ;
+---------------------------------------+-----------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 45    ;
; Number of registers using Synchronous Clear  ; 34    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |SIN|VAL_Freq_Set[4]       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon Oct 27 16:50:55 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SIN -c SIN
Info: Found 2 design units, including 1 entities, in source file SIN.vhd
    Info: Found design unit 1: SIN-using_std_logic
    Info: Found entity 1: SIN
Info: Elaborating entity "SIN" for the top level hierarchy
Info: Duplicate registers merged to single register
    Info: Duplicate register "VAL_Freq_Set[1]" merged to single register "VAL_Freq_Set[0]"
    Info: Duplicate register "VAL_Freq_Set[2]" merged to single register "VAL_Freq_Set[0]"
    Info: Duplicate register "VAL_Freq_Set[3]" merged to single register "VAL_Freq_Set[0]"
    Info: Duplicate register "VAL_Freq_Set[8]" merged to single register "VAL_Freq_Set[4]"
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus Signal_Freq_Out~1 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus Signal_RUN_DIS~1 that it feeds
Info: One or more bidirs are fed by always enabled tri-state buffers
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "Signal_Freq_Out" is moved to its source
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "Signal_RUN_DIS" is moved to its source
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "Signal_Freq_Out~10"
    Warning: Node "Signal_RUN_DIS~10"
Info: Implemented 68 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 0 output pins
    Info: Implemented 2 bidirectional pins
    Info: Implemented 61 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Mon Oct 27 16:51:05 2008
    Info: Elapsed time: 00:00:10