vga.vhd.bak

几个SPI

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--*************************************************************************************************
--  CreateDate  :  2007-08-20 
--  ModifData   :  2007-08-20 
--  Description :  VGA Interface 
--  Author      :  Explorer01 
--  Version     :  V1.0  
--*************************************************************************************************
---------------------------------------------------------------------------------------------------

-- VHDL library Declarations 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

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---------------------------------------------------------------------------------------------------
-- The Entity Declarations 
ENTITY VGA IS
	PORT 
	(
		RESET	: IN STD_LOGIC;
		CLK		: IN STD_LOGIC; 
		CLKTemp	: IN STD_LOGIC; 
		
		-------------------------------------
		-- VGA 
		R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		
		VS : OUT STD_LOGIC; 
		HS : OUT STD_LOGIC
	);
END VGA;

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-- The Architecture of Entity Declarations 
ARCHITECTURE Behavioral OF VGA IS
--	SuperVGA timing from NEC monitor manual
--	Horizontal :
--	                ______________                 _____________
--	               |              |               |
--	_______________|  VIDEO       |_______________|  VIDEO (next line)
--	
--	___________   _____________________   ______________________
--	           |_|                     |_|
--	            B C <------D-----><-E->
--	            <----------A---------->
--	
--	
--	Vertical :
--	                ______________                 _____________
--	               |              |               |           
--	_______________|  VIDEO       |_______________|  VIDEO (next frame)
--	
--	___________   _____________________   ______________________
--	           |_|                     |_|
--	            P Q <------R-----><-S->
--	            <----------O---------->
--	
--	For VESA 800*600 @ 60Hz:
--	Fh (kHz) :37.88
--	A  (us)  :26.4
--	B  (us)  :3.2
--	C  (us)  :2.2
--	D  (us)  :20.0
--	E  (us)  :1.0
--	
--	Fv (Hz)  :60.32
--	O  (ms)  :16.579
--	P  (ms)  :0.106
--	Q  (ms)  :0.607
--	R  (ms)  :15.84
--	S  (ms)  :0.026
--	
--	
--	Horizonal timing information:
--	
--	Mode name          Pixel      sync      back  active  front whole line
--	                   clock      pulse     porch  time   porch  period
--	                   (MHz)   (us)  (pix)  (pix)  (pix)  (pix)  (pix)
--	 
--	VGA 800x600 60Hz   40       3.2   128     85    806    37    1056
--	
--	Vertical timing information:
--	Mode name          Lines   line    sync      back        active     front     whole frame
--	                   Total   width   pulse     porch        time      porch        period
--	                           (us)   (us)(lin) (us)(lin)  (us)  (lin)  (us)(lin)  (us)  (lin)
--	
--	VGA 800x600 60Hz    628    26.40  106   4   554   21   15945  604         -1*  16579  628
--	
	------------------------------------------------
	CONSTANT H_PIXELS		: INTEGER := 640; 	--  806
	CONSTANT H_FRONTPORCH	: INTEGER := 16; 	--  37
	CONSTANT H_SYNCTIME		: INTEGER := 96; 	--  128
	CONSTANT H_BACKPORCH	: INTEGER := 48; 	--  85
	CONSTANT H_SYNCSTART	: INTEGER := H_PIXELS    + H_FRONTPORCH; 
	CONSTANT H_SYNCEND		: INTEGER := H_SYNCSTART + H_SYNCTIME; 
	CONSTANT H_PERIOD		: INTEGER := H_SYNCEND   + H_BACKPORCH; 
	
	CONSTANT V_LINES		: INTEGER := 480; 	--  604
	CONSTANT V_FRONTPORCH	: INTEGER := 11; 	--  -1
	CONSTANT V_SYNCTIME		: INTEGER := 2; 	--  4
	CONSTANT V_BACKPORCH	: INTEGER := 32; 	--  21
	CONSTANT V_SYNCSTART	: INTEGER := V_LINES     + V_FRONTPORCH; 
	CONSTANT V_SYNCEND		: INTEGER := V_SYNCSTART + V_SYNCTIME; 
	CONSTANT V_PERIOD		: INTEGER := V_SYNCEND   + V_BACKPORCH; 
	
	------------------------------------------------
	------------------------------------------------
	SIGNAL HsyncB : STD_LOGIC; 
	SIGNAL VsyncB : STD_LOGIC; 
	SIGNAL Hcnt	: STD_LOGIC_VECTOR(9 DOWNTO 0); 
	SIGNAL Vcnt	: STD_LOGIC_VECTOR(9 DOWNTO 0); 
	
	SIGNAL Enable : STD_LOGIC; 
	SIGNAL TempR  : STD_LOGIC; 
	SIGNAL TempG  : STD_LOGIC; 
	SIGNAL TempB  : STD_LOGIC; 
	SIGNAL ColorR : STD_LOGIC_VECTOR(3 DOWNTO 0); 
	SIGNAL ColorG : STD_LOGIC_VECTOR(3 DOWNTO 0); 
	SIGNAL ColorB : STD_LOGIC_VECTOR(3 DOWNTO 0); 
	
	------------------------------------------------
	------------------------------------------------
	SIGNAL Count : STD_LOGIC_VECTOR(2 DOWNTO 0); 
	
BEGIN
	
	--==============================================
	-- Clock process 
	------------------------------------------------
	-- Horizontal counter 
	PROCESS( RESET, CLK )
	BEGIN 
		IF( RESET='0' ) THEN Hcnt <= (OTHERS=>'0');
		ELSIF( CLK'EVENT AND CLK='1' ) THEN  
			IF( Hcnt<H_PERIOD ) THEN Hcnt <= Hcnt + 1; 
			ELSE 					 Hcnt <= (OTHERS=>'0');
			END IF; 
		END IF; 
	END PROCESS; 
	
	------------------------------------------------
	-- Vertical counter 
	PROCESS( RESET, HsyncB )
	BEGIN
		IF( RESET='0' ) THEN Vcnt <= (OTHERS=>'0');
		ELSIF( HsyncB'EVENT AND HsyncB='1' ) THEN  
			IF( Vcnt<V_PERIOD ) THEN Vcnt <= Vcnt + 1; 
			ELSE 					 Vcnt <= (OTHERS=>'0');
			END IF; 
		END IF; 
	END PROCESS; 
	
	------------------------------------------------
	------------------------------------------------
	-- Horizontal Sync 
	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET='0' ) THEN HsyncB <= '1';
		ELSIF( CLK'EVENT AND CLK='1' ) THEN  
			IF( Hcnt>=(H_PIXELS + H_FRONTPORCH) AND Hcnt<(H_PIXELS + H_FRONTPORCH + H_SYNCTIME) ) THEN 
				HsyncB <= '0';
			ELSE 
				HsyncB <= '1';
			END IF; 
		END IF; 
	END PROCESS; 
	
	------------------------------------------------
	-- Vertical Sync 
	PROCESS( RESET, HsyncB )
	BEGIN
		IF( RESET='0' ) THEN VsyncB <= '1';
		ELSIF( HsyncB'EVENT AND HsyncB='1' ) THEN  
			IF( Vcnt>=(V_LINES + V_FRONTPORCH) AND Vcnt<(V_LINES + V_FRONTPORCH + V_SYNCTIME) ) THEN 
				VsyncB <= '0';
			ELSE 
				VsyncB <= '1';
			END IF; 
		END IF; 
	END PROCESS; 
	
	HS <= HsyncB; 
	VS <= VsyncB; 
	
	--==============================================
	------------------------------------------------
	-- 
	PROCESS( RESET, CLK, Hcnt, Vcnt )
	BEGIN
		IF( CLK'EVENT AND CLK='1' ) THEN 
			IF	 ( RESET='0' 						) THEN 	Enable <= '0';
			ELSIF( Hcnt>=H_PIXELS OR Vcnt>=V_LINES 	) THEN 	Enable <= '0';
			ELSE 											Enable <= '1';
			END IF; 
		END IF; 
	END PROCESS; 
	
	------------------------------------------------
	-- 
	PROCESS( RESET, CLKTemp, Hcnt, Vcnt, Enable, TempR, TempG, TempB, Count )
	BEGIN
		IF   ( RESET='0' 					 ) THEN Count <= "000";
		ELSIF( CLKTemp'EVENT AND CLKTemp='1' ) THEN Count <= Count + 1; 
		END IF; 
		
		------------------------------------------------
		CASE Hcnt(7 DOWNTO 5) IS 
			WHEN "000" => TempR <= '1'; TempG <= '1'; TempB <= '1'; 
			WHEN "001" => TempR <= '0'; TempG <= '0'; TempB <= '0'; 
			WHEN "010" => TempR <= '1'; TempG <= '0'; TempB <= '0'; 
			WHEN "011" => TempR <= '0'; TempG <= '0'; TempB <= '1'; 
			WHEN "100" => TempR <= '0'; TempG <= '1'; TempB <= '0'; 
			WHEN "101" => TempR <= '1'; TempG <= '0'; TempB <= '1'; 
			WHEN "110" => TempR <= '1'; TempG <= '1'; TempB <= '0'; 
			WHEN "111" => TempR <= '1'; TempG <= '1'; TempB <= '1'; 
			WHEN OTHERS=> TempR <= '0'; TempG <= '0'; TempB <= '0'; 
		END CASE; 
		
		IF( Enable='1' ) THEN 
			IF( TempR='1' ) THEN R <= Count & '1'; 
			ELSE 				 R <= (OTHERS=>'0'); 
			END IF; 
			IF( TempG='1' ) THEN G <= '1' & Count; 
			ELSE 				 G <= (OTHERS=>'0'); 
			END IF; 
			IF( TempB='1' ) THEN B <= '1' & Count(0) & Count(1) & Count(2); 
			ELSE 				 B <= (OTHERS=>'0'); 
			END IF; 
		ELSE 
			R <= (OTHERS=>'0'); 
			G <= (OTHERS=>'0'); 
			B <= (OTHERS=>'0'); 
		END IF; 
	END PROCESS; 
	-------------------------------------------------
	-------------------------------------------------
	
END Behavioral;