📄 pll_waveforms.html
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<title>Sample Waveforms for pll.tdf </title>
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<h2><CENTER>Sample behavioral waveforms for design file pll.tdf </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll.tdf. The design pll.tdf has Cyclone AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 25000 ps. CLK0 multiply by = 1, CLK0 divide by = 2, CLK0 phase_shift = 0 Output port LOCKED is used. This port will go high when the PLL locks to the input clock. </P>
<CENTER><img src=pll_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
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