colorled32.tan.rpt

这是一个用于32位色控制的LED大屏幕的AHDL代码

+-----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Worst-case tsu                                            ; N/A       ; None                             ; 8.925 ns                                       ; vsync                                                                                                             ; digitalfilter:vsynfilter|datadff[0]                                                                               ; --                                         ; inclk                                      ; 0            ;
; Worst-case tco                                            ; N/A       ; None                             ; 39.010 ns                                      ; convertdff0[14][21]                                                                                               ; led[14]                                                                                                           ; inclk                                      ; --                                         ; 0            ;
; Worst-case tpd                                            ; N/A       ; None                             ; 10.086 ns                                      ; hsync                                                                                                             ; free55                                                                                                            ; --                                         ; --                                         ; 0            ;
; Worst-case th                                             ; N/A       ; None                             ; -0.987 ns                                      ; in_blu[4]                                                                                                         ; dpram1024x32:wrram|altsyncram:altsyncram_component|altsyncram_mhh1:auto_generated|ram_block1a27~porta_datain_reg2 ; --                                         ; pclk                                       ; 0            ;
; Clock Setup: '4x40pll:4pll|altpll:altpll_component|_clk0' ; 3.134 ns  ; 160.00 MHz ( period = 6.250 ns ) ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 10count:inrowcnt|lpm_counter:lpm_counter_component|cntr_lvi:auto_generated|safe_q[1]                              ; 10count:inrowcnt|lpm_counter:lpm_counter_component|cntr_lvi:auto_generated|safe_q[9]                              ; 4x40pll:4pll|altpll:altpll_component|_clk0 ; 4x40pll:4pll|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'inclk'                                      ; 14.568 ns ; 40.00 MHz ( period = 25.000 ns ) ; 95.86 MHz ( period = 10.432 ns )               ; dpram1024x32:wrram|altsyncram:altsyncram_component|altsyncram_mhh1:auto_generated|ram_block1a2~portb_address_reg9 ; convertdff1[7][2]                                                                                                 ; inclk                                      ; inclk                                      ; 0            ;
; Clock Setup: 'pclk'                                       ; N/A       ; None                             ; 152.07 MHz ( period = 6.576 ns )               ; vervalid                                                                                                          ; dpram1024x32:wrram|altsyncram:altsyncram_component|altsyncram_mhh1:auto_generated|ram_block1a27~porta_datain_reg3 ; pclk                                       ; pclk                                       ; 0            ;
; Clock Hold: 'inclk'                                       ; -7.911 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A                                            ; out2led                                                                                                           ; out2led                                                                                                           ; inclk                                      ; inclk                                      ; 1441         ;
; Clock Hold: '4x40pll:4pll|altpll:altpll_component|_clk0'  ; 0.734 ns  ; 160.00 MHz ( period = 6.250 ns ) ; N/A                                            ; 10count:inrowcnt|lpm_counter:lpm_counter_component|cntr_lvi:auto_generated|safe_q[4]                              ; 10count:inrowcnt|lpm_counter:lpm_counter_component|cntr_lvi:auto_generated|safe_q[4]                              ; 4x40pll:4pll|altpll:altpll_component|_clk0 ; 4x40pll:4pll|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                              ;           ;                                  ;                                                ;                                                                                                                   ;                                                                                                                   ;                                            ;                                            ; 1441         ;
+-----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; 4x40pll:4pll|altpll:altpll_component|_clk0 ;                    ; PLL output ; 160.0 MHz        ; 0.000 ns      ; 0.000 ns     ; inclk    ; 4                     ; 1                   ; -1.885 ns ;              ;
; inclk                                      ;                    ; User Pin   ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; pclk                                       ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;