colorled32.map.rpt

这是一个用于32位色控制的LED大屏幕的AHDL代码

Analysis & Synthesis report for colorled32
Sun May 20 09:23:38 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Removed During Synthesis
  9. General Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for dpram1024x32:wrram|altsyncram:altsyncram_component|altsyncram_mhh1:auto_generated
 12. Parameter Settings for User Entity Instance: 4count:fd|lpm_counter:lpm_counter_component
 13. Parameter Settings for User Entity Instance: 12count:wrincnt|lpm_counter:lpm_counter_component
 14. Parameter Settings for User Entity Instance: 12count:framecnt|lpm_counter:lpm_counter_component
 15. Parameter Settings for User Entity Instance: 10count:inrowcnt|lpm_counter:lpm_counter_component
 16. Parameter Settings for User Entity Instance: 12count:outcnt|lpm_counter:lpm_counter_component
 17. Parameter Settings for User Entity Instance: 12count:incolcnt|lpm_counter:lpm_counter_component
 18. Parameter Settings for User Entity Instance: 12count:ledcnt|lpm_counter:lpm_counter_component
 19. Parameter Settings for User Entity Instance: 4x40pll:4pll
 20. Parameter Settings for User Entity Instance: 4x40pll:4pll|altpll:altpll_component
 21. Parameter Settings for User Entity Instance: dpram1024x32:wrram
 22. Parameter Settings for User Entity Instance: dpram1024x32:wrram|altsyncram:altsyncram_component
 23. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun May 20 09:23:38 2007    ;
; Quartus II Version          ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name               ; colorled32                               ;
; Top-level Entity Name       ; colorled32                               ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 3,564                                    ;
; Total pins                  ; 173                                      ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 32,768                                   ;
; Total PLLs                  ; 1                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1C6Q240C8        ;                    ;
; Top-level entity name                                              ; colorled32         ; colorled32         ;
; Family name                                                        ; Cyclone            ; Stratix            ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                  ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                  ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K/M9K Memory Blocks                            ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM/M144K Memory Blocks                        ; Unlimited          ; Unlimited          ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;