colorled32.fit.rpt

这是一个用于32位色控制的LED大屏幕的AHDL代码

; Timing Models         ; Final                                    ;
; Total logic elements  ; 2,537 / 5,980 ( 42 % )                   ;
; Total pins            ; 173 / 185 ( 94 % )                       ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 32,768 / 92,160 ( 36 % )                 ;
; Total PLLs            ; 1 / 2 ( 50 % )                           ;
+-----------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C6Q240C8                    ;                                ;
; Fit Attempts to Skip                               ; 0                              ; 0.0                            ;
; Use TimeQuest Timing Analyzer                      ; Off                            ;                                ;
; Router Timing Optimization Level                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining             ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
; Stop After Congestion Map Generation               ; Off                            ; Off                            ;
; Use smart compilation                              ; Off                            ; Off                            ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/nofa/桌面/colorled/colorled32.pin.


+----------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                    ;
+---------------------------------------------+------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                              ;
+---------------------------------------------+------------------------------------------------------------------------------------+
; Total logic elements                        ; 2,537 / 5,980 ( 42 % )                                                             ;
;     -- Combinational with no register       ; 421                                                                                ;
;     -- Register only                        ; 1028                                                                               ;
;     -- Combinational with a register        ; 1088                                                                               ;
;                                             ;                                                                                    ;
; Logic element usage by number of LUT inputs ;                                                                                    ;
;     -- 4 input functions                    ; 1436                                                                               ;
;     -- 3 input functions                    ; 5                                                                                  ;
;     -- 2 input functions                    ; 54                                                                                 ;