colorled32.tan.summary

这是一个用于32位色控制的LED大屏幕的AHDL代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.925 ns
From           : vsync
To             : digitalfilter:vsynfilter|datadff[0]
From Clock     : --
To Clock       : inclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 39.010 ns
From           : convertdff0[14][21]
To             : led[14]
From Clock     : inclk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.086 ns
From           : hsync
To             : free55
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.987 ns
From           : in_blu[4]
To             : dpram1024x32:wrram|altsyncram:altsyncram_component|altsyncram_mhh1:auto_generated|ram_block1a27~porta_datain_reg2
From Clock     : --
To Clock       : pclk
Failed Paths   : 0

Type           : Clock Setup: '4x40pll:4pll|altpll:altpll_component|_clk0'
Slack          : 3.134 ns
Required Time  : 160.00 MHz ( period = 6.250 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : 10count:inrowcnt|lpm_counter:lpm_counter_component|cntr_lvi:auto_generated|safe_q[1]
To             : 10count:inrowcnt|lpm_counter:lpm_counter_component|cntr_lvi:auto_generated|safe_q[9]
From Clock     : 4x40pll:4pll|altpll:altpll_component|_clk0
To Clock       : 4x40pll:4pll|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'inclk'
Slack          : 14.568 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : 95.86 MHz ( period = 10.432 ns )
From           : dpram1024x32:wrram|altsyncram:altsyncram_component|altsyncram_mhh1:auto_generated|ram_block1a2~portb_address_reg9
To             : convertdff1[7][2]
From Clock     : inclk
To Clock       : inclk
Failed Paths   : 0

Type           : Clock Setup: 'pclk'
Slack          : N/A
Required Time  : None
Actual Time    : 152.07 MHz ( period = 6.576 ns )
From           : vervalid
To             : dpram1024x32:wrram|altsyncram:altsyncram_component|altsyncram_mhh1:auto_generated|ram_block1a27~porta_datain_reg3
From Clock     : pclk
To Clock       : pclk
Failed Paths   : 0

Type           : Clock Hold: 'inclk'
Slack          : -7.911 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : out2led
To             : out2led
From Clock     : inclk
To Clock       : inclk
Failed Paths   : 1441

Type           : Clock Hold: '4x40pll:4pll|altpll:altpll_component|_clk0'
Slack          : 0.734 ns
Required Time  : 160.00 MHz ( period = 6.250 ns )
Actual Time    : N/A
From           : 10count:inrowcnt|lpm_counter:lpm_counter_component|cntr_lvi:auto_generated|safe_q[4]
To             : 10count:inrowcnt|lpm_counter:lpm_counter_component|cntr_lvi:auto_generated|safe_q[4]
From Clock     : 4x40pll:4pll|altpll:altpll_component|_clk0
To Clock       : 4x40pll:4pll|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1441

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