cpu.map.rpt

这是接上面程序

+------------------------+---------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 8           ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_4ih ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_2 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 9           ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_5ih ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/12-microprogram controller/CPU.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Aug 23 16:34:15 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CPU -c CPU
Info: Found 2 design units, including 0 entities, in source file cpu_defs.vhd
    Info: Found design unit 1: cpu_defs
    Info: Found design unit 2: cpu_defs-body
Info: Found 2 design units, including 1 entities, in source file cpu.vhd
    Info: Found design unit 1: CPU-rtl
    Info: Found entity 1: CPU
Info: Elaborating entity "CPU" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at cpu.vhd(65): object "microcode" declared but not used
Warning: VHDL Process Statement warning at cpu.vhd(180): signal "sysbus_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(182): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(184): signal "acc_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(186): signal "IR_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(188): signal "mar_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(190): signal "mdr_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(192): signal "mem" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "count[0]~10"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
    Info: Duplicate register "data_r_out[9]~reg0" merged to single register "data_r_out[3]~reg0"
    Info: Duplicate register "data_r_out[16]~reg0" merged to single register "data_r_out[10]~reg0"
    Info: Duplicate register "data_r_out[18]~reg0" merged to single register "data_r_out[12]~reg0"
    Info: Duplicate register "op[0]" merged to single register "IR_out[5]"
    Info: Duplicate register "op[1]" merged to single register "IR_out[6]"
    Info: Duplicate register "op[2]" merged to single register "IR_out[7]"
Info: Registers with preset signals will power-up high
Info: Implemented 929 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 36 output pins
    Info: Implemented 883 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Processing ended: Tue Aug 23 16:34:26 2005
    Info: Elapsed time: 00:00:12