cpu.map.eqn

这是接上面程序

--A1L921 is add_r~498
--operation mode is normal

A1L921 = A1L421 & !z_flag & !A1L889 # !A1L789;


--A1L621 is add_r~488
--operation mode is normal

A1L621 = A1L889 # z_flag & A1L421;

--A1L031 is add_r~499
--operation mode is normal

A1L031 = A1L889 # z_flag & A1L421;


--A1L721 is add_r~490
--operation mode is normal

A1L721 = A1L989 $ (A1L889 # !A1L421);

--A1L131 is add_r~500
--operation mode is normal

A1L131 = A1L989 $ (A1L889 # !A1L421);


--A1L699 is Mux~2795
--operation mode is normal

A1L699 = add_r[1] & add_r[2] & !add_r[3] & !add_r[0];

--A1L1731 is Mux~3193
--operation mode is normal

A1L1731 = add_r[1] & add_r[2] & !add_r[3] & !add_r[0];


--A1L799 is Mux~2796
--operation mode is normal

A1L799 = !add_r[2] & !add_r[0] & !add_r[1] & !add_r[3];

--A1L2731 is Mux~3194
--operation mode is normal

A1L2731 = !add_r[2] & !add_r[0] & !add_r[1] & !add_r[3];


--A1L899 is Mux~2797
--operation mode is normal

A1L899 = add_r[0] & add_r[3] & !add_r[2] & !add_r[1];

--A1L3731 is Mux~3195
--operation mode is normal

A1L3731 = add_r[0] & add_r[3] & !add_r[2] & !add_r[1];


--A1L999 is Mux~2798
--operation mode is normal

A1L999 = add_r[1] & !add_r[3] & !add_r[0] & !add_r[2];

--A1L4731 is Mux~3196
--operation mode is normal

A1L4731 = add_r[1] & !add_r[3] & !add_r[0] & !add_r[2];


--A1L0001 is Mux~2799
--operation mode is normal

A1L0001 = add_r[2] & !add_r[0] & !add_r[1] & !add_r[3];

--A1L5731 is Mux~3197
--operation mode is normal

A1L5731 = add_r[2] & !add_r[0] & !add_r[1] & !add_r[3];


--mdr[5] is mdr[5]
--operation mode is normal

mdr[5]_lut_out = A1L913 # A1L93 & A1L899 & A1L399;
mdr[5] = DFFEA(mdr[5]_lut_out, clock, reset, , , , );

--A1L492Q is mdr[5]~2381
--operation mode is normal

A1L492Q = mdr[5];


--instr_reg[5] is instr_reg[5]
--operation mode is normal

instr_reg[5]_lut_out = A1L999 & mdr[5] # !A1L999 & (instr_reg[5]);
instr_reg[5] = DFFEA(instr_reg[5]_lut_out, clock, reset, , , , );

--A1L832Q is instr_reg[5]~360
--operation mode is normal

A1L832Q = instr_reg[5];


--mdr[6] is mdr[6]
--operation mode is normal

mdr[6]_lut_out = A1L223 # A1L24 & A1L899 & A1L399;
mdr[6] = DFFEA(mdr[6]_lut_out, clock, reset, , , , );

--A1L692Q is mdr[6]~2382
--operation mode is normal

A1L692Q = mdr[6];


--instr_reg[6] is instr_reg[6]
--operation mode is normal

instr_reg[6]_lut_out = A1L999 & mdr[6] # !A1L999 & (instr_reg[6]);
instr_reg[6] = DFFEA(instr_reg[6]_lut_out, clock, reset, , , , );

--A1L042Q is instr_reg[6]~361
--operation mode is normal

A1L042Q = instr_reg[6];


--mdr[7] is mdr[7]
--operation mode is normal

mdr[7]_lut_out = A1L523 # A1L54 & A1L899 & A1L399;
mdr[7] = DFFEA(mdr[7]_lut_out, clock, reset, , , , );

--A1L892Q is mdr[7]~2383
--operation mode is normal

A1L892Q = mdr[7];


--instr_reg[7] is instr_reg[7]
--operation mode is normal

instr_reg[7]_lut_out = A1L999 & mdr[7] # !A1L999 & (instr_reg[7]);
instr_reg[7] = DFFEA(instr_reg[7]_lut_out, clock, reset, , , , );

--A1L242Q is instr_reg[7]~362
--operation mode is normal

A1L242Q = instr_reg[7];


--mdr_out[0] is mdr_out[0]
--operation mode is normal

mdr_out[0]_lut_out = A1L923;
mdr_out[0] = DFFEA(mdr_out[0]_lut_out, clock, , , reset, , );

--A1L103Q is mdr_out[0]~40
--operation mode is normal

A1L103Q = mdr_out[0];


--mar_out[0] is mar_out[0]
--operation mode is normal

mar_out[0]_lut_out = A1L399 & (mar[0]) # !A1L399 & A1L8971;
mar_out[0] = DFFEA(mar_out[0]_lut_out, clock, , , reset, , );

--A1L372Q is mar_out[0]~35
--operation mode is normal

A1L372Q = mar_out[0];


--A1L1001 is Mux~2800
--operation mode is normal

A1L1001 = mode[0] & mdr_out[0] # !mode[0] & (mar_out[0]);

--A1L6731 is Mux~3198
--operation mode is normal

A1L6731 = mode[0] & mdr_out[0] # !mode[0] & (mar_out[0]);


--G1_q[0] is lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

G1_q[0]_lut_out = ((A1L799 $ G1_q[0] & A1L091) # (mdr[0] & !A1L091)) & VCC;
G1_q[0] = DFFEA(G1_q[0]_lut_out, clock, reset, , , , );

--G1L31Q is lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

G1L31Q = G1_q[0];

--G1L3 is lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

G1L3 = CARRY(G1_q[0]);


--acc_out[0] is acc_out[0]
--operation mode is normal

acc_out[0]_lut_out = A1L64 # A1L861 & A1L74;
acc_out[0] = DFFEA(acc_out[0]_lut_out, clock, , , reset, , );

--A1L22Q is acc_out[0]~72
--operation mode is normal

A1L22Q = acc_out[0];


--sysbus[0] is sysbus[0]
--operation mode is normal

sysbus[0]_lut_out = A1L299 & A1L923 # !A1L299 & (A1L8971);
sysbus[0] = DFFEA(sysbus[0]_lut_out, clock, reset, , , , );

--A1L1871Q is sysbus[0]~2665
--operation mode is normal

A1L1871Q = sysbus[0];


--A1L2001 is Mux~2801
--operation mode is normal

A1L2001 = mode[0] & (mode[1]) # !mode[0] & (mode[1] & acc_out[0] # !mode[1] & (sysbus[0]));

--A1L7731 is Mux~3199
--operation mode is normal

A1L7731 = mode[0] & (mode[1]) # !mode[0] & (mode[1] & acc_out[0] # !mode[1] & (sysbus[0]));


--IR_out[0] is IR_out[0]
--operation mode is normal

IR_out[0]_lut_out = A1L999 & (mdr[0]) # !A1L999 & instr_reg[0];
IR_out[0] = DFFEA(IR_out[0]_lut_out, clock, , , reset, , );

--A1L542Q is IR_out[0]~43
--operation mode is normal

A1L542Q = IR_out[0];


--A1L3001 is Mux~2802
--operation mode is normal

A1L3001 = mode[0] & (A1L2001 & (IR_out[0]) # !A1L2001 & G1_q[0]) # !mode[0] & (A1L2001);

--A1L8731 is Mux~3200
--operation mode is normal

A1L8731 = mode[0] & (A1L2001 & (IR_out[0]) # !A1L2001 & G1_q[0]) # !mode[0] & (A1L2001);


--A1L4001 is Mux~2803
--operation mode is normal

A1L4001 = mode[2] & (mode[1] # !A1L1001) # !mode[2] & (!A1L3001);

--A1L9731 is Mux~3201
--operation mode is normal

A1L9731 = mode[2] & (mode[1] # !A1L1001) # !mode[2] & (!A1L3001);

--A1L0831 is Mux~3202
--operation mode is normal

A1L0831 = mode[2] & (mode[1] # !A1L1001) # !mode[2] & (!A1L3001);


--mem[22][0] is mem[22][0]
--operation mode is normal

mem[22][0]_lut_out = mdr[0];
mem[22][0] = DFFEA(mem[22][0]_lut_out, clock, reset, , A1L887, , );

--A1L987Q is mem[22][0]~1314
--operation mode is normal

A1L987Q = mem[22][0];


--mem[26][0] is mem[26][0]
--operation mode is normal

mem[26][0]_lut_out = mdr[0];
mem[26][0] = DFFEA(mem[26][0]_lut_out, clock, reset, , A1L468, , );

--A1L568Q is mem[26][0]~1315
--operation mode is normal

A1L568Q = mem[26][0];


--mem[18][0] is mem[18][0]
--operation mode is normal

mem[18][0]_lut_out = mdr[0];
mem[18][0] = DFFEA(mem[18][0]_lut_out, clock, reset, , A1L217, , );

--A1L317Q is mem[18][0]~1316
--operation mode is normal

A1L317Q = mem[18][0];


--A1L5001 is Mux~2804
--operation mode is normal

A1L5001 = mem_addr[2] & (mem_addr[3]) # !mem_addr[2] & (mem_addr[3] & mem[26][0] # !mem_addr[3] & (mem[18][0]));

--A1L1831 is Mux~3203
--operation mode is normal

A1L1831 = mem_addr[2] & (mem_addr[3]) # !mem_addr[2] & (mem_addr[3] & mem[26][0] # !mem_addr[3] & (mem[18][0]));


--mem[30][0] is mem[30][0]
--operation mode is normal

mem[30][0]_lut_out = mdr[0];
mem[30][0] = DFFEA(mem[30][0]_lut_out, clock, reset, , A1L049, , );

--A1L149Q is mem[30][0]~1317
--operation mode is normal

A1L149Q = mem[30][0];


--A1L6001 is Mux~2805
--operation mode is normal

A1L6001 = mem_addr[2] & (A1L5001 & (mem[30][0]) # !A1L5001 & mem[22][0]) # !mem_addr[2] & (A1L5001);

--A1L2831 is Mux~3204
--operation mode is normal

A1L2831 = mem_addr[2] & (A1L5001 & (mem[30][0]) # !A1L5001 & mem[22][0]) # !mem_addr[2] & (A1L5001);


--mem[25][0] is mem[25][0]
--operation mode is normal

mem[25][0]_lut_out = mdr[0];
mem[25][0] = DFFEA(mem[25][0]_lut_out, clock, reset, , A1L548, , );

--A1L648Q is mem[25][0]~1318
--operation mode is normal

A1L648Q = mem[25][0];


--mem[21][0] is mem[21][0]
--operation mode is normal

mem[21][0]_lut_out = mdr[0];
mem[21][0] = DFFEA(mem[21][0]_lut_out, clock, reset, , A1L967, , );

--A1L077Q is mem[21][0]~1319
--operation mode is normal

A1L077Q = mem[21][0];


--mem[17][0] is mem[17][0]
--operation mode is normal

mem[17][0]_lut_out = mdr[0];
mem[17][0] = DFFEA(mem[17][0]_lut_out, clock, reset, , A1L396, , );

--A1L496Q is mem[17][0]~1320
--operation mode is normal

A1L496Q = mem[17][0];


--A1L7001 is Mux~2806
--operation mode is normal

A1L7001 = mem_addr[3] & (mem_addr[2]) # !mem_addr[3] & (mem_addr[2] & mem[21][0] # !mem_addr[2] & (mem[17][0]));

--A1L3831 is Mux~3205
--operation mode is normal

A1L3831 = mem_addr[3] & (mem_addr[2]) # !mem_addr[3] & (mem_addr[2] & mem[21][0] # !mem_addr[2] & (mem[17][0]));


--mem[29][0] is mem[29][0]
--operation mode is normal

mem[29][0]_lut_out = mdr[0];
mem[29][0] = DFFEA(mem[29][0]_lut_out, clock, reset, , A1L129, , );

--A1L229Q is mem[29][0]~1321
--operation mode is normal

A1L229Q = mem[29][0];


--A1L8001 is Mux~2807
--operation mode is normal

A1L8001 = mem_addr[3] & (A1L7001 & (mem[29][0]) # !A1L7001 & mem[25][0]) # !mem_addr[3] & (A1L7001);

--A1L4831 is Mux~3206
--operation mode is normal

A1L4831 = mem_addr[3] & (A1L7001 & (mem[29][0]) # !A1L7001 & mem[25][0]) # !mem_addr[3] & (A1L7001);


--mem[20][0] is mem[20][0]
--operation mode is normal

mem[20][0]_lut_out = mdr[0];
mem[20][0] = DFFEA(mem[20][0]_lut_out, clock, reset, , A1L057, , );

--A1L157Q is mem[20][0]~1322
--operation mode is normal

A1L157Q = mem[20][0];


--mem[24][0] is mem[24][0]
--operation mode is normal

mem[24][0]_lut_out = mdr[0];
mem[24][0] = DFFEA(mem[24][0]_lut_out, clock, reset, , A1L628, , );

--A1L728Q is mem[24][0]~1323
--operation mode is normal

A1L728Q = mem[24][0];


--mem[16][0] is mem[16][0]
--operation mode is normal

mem[16][0]_lut_out = mdr[0];
mem[16][0] = DFFEA(mem[16][0]_lut_out, clock, reset, , A1L476, , );

--A1L576Q is mem[16][0]~1324
--operation mode is normal

A1L576Q = mem[16][0];


--A1L9001 is Mux~2808
--operation mode is normal

A1L9001 = mem_addr[2] & (mem_addr[3]) # !mem_addr[2] & (mem_addr[3] & mem[24][0] # !mem_addr[3] & (mem[16][0]));

--A1L5831 is Mux~3207
--operation mode is normal

A1L5831 = mem_addr[2] & (mem_addr[3]) # !mem_addr[2] & (mem_addr[3] & mem[24][0] # !mem_addr[3] & (mem[16][0]));


--mem[28][0] is mem[28][0]
--operation mode is normal

mem[28][0]_lut_out = mdr[0];
mem[28][0] = DFFEA(mem[28][0]_lut_out, clock, reset, , A1L209, , );

--A1L309Q is mem[28][0]~1325
--operation mode is normal

A1L309Q = mem[28][0];


--A1L0101 is Mux~2809
--operation mode is normal

A1L0101 = mem_addr[2] & (A1L9001 & (mem[28][0]) # !A1L9001 & mem[20][0]) # !mem_addr[2] & (A1L9001);

--A1L6831 is Mux~3208
--operation mode is normal

A1L6831 = mem_addr[2] & (A1L9001 & (mem[28][0]) # !A1L9001 & mem[20][0]) # !mem_addr[2] & (A1L9001);


--A1L1101 is Mux~2810
--operation mode is normal

A1L1101 = mem_addr[1] & (mem_addr[0]) # !mem_addr[1] & (mem_addr[0] & A1L8001 # !mem_addr[0] & (A1L0101));

--A1L7831 is Mux~3209
--operation mode is normal

A1L7831 = mem_addr[1] & (mem_addr[0]) # !mem_addr[1] & (mem_addr[0] & A1L8001 # !mem_addr[0] & (A1L0101));


--mem[27][0] is mem[27][0]
--operation mode is normal

mem[27][0]_lut_out = mdr[0];
mem[27][0] = DFFEA(mem[27][0]_lut_out, clock, reset, , A1L388, , );

--A1L488Q is mem[27][0]~1326
--operation mode is normal

A1L488Q = mem[27][0];


--mem[23][0] is mem[23][0]
--operation mode is normal

mem[23][0]_lut_out = mdr[0];
mem[23][0] = DFFEA(mem[23][0]_lut_out, clock, reset, , A1L708, , );

--A1L808Q is mem[23][0]~1327
--operation mode is normal

A1L808Q = mem[23][0];


--mem[19][0] is mem[19][0]
--operation mode is normal

mem[19][0]_lut_out = mdr[0];
mem[19][0] = DFFEA(mem[19][0]_lut_out, clock, reset, , A1L137, , );

--A1L237Q is mem[19][0]~1328
--operation mode is normal

A1L237Q = mem[19][0];


--A1L2101 is Mux~2811
--operation mode is normal

A1L2101 = mem_addr[3] & (mem_addr[2]) # !mem_addr[3] & (mem_addr[2] & mem[23][0] # !mem_addr[2] & (mem[19][0]));

--A1L8831 is Mux~3210
--operation mode is normal

A1L8831 = mem_addr[3] & (mem_addr[2]) # !mem_addr[3] & (mem_addr[2] & mem[23][0] # !mem_addr[2] & (mem[19][0]));


--mem[31][0] is mem[31][0]
--operation mode is normal

mem[31][0]_lut_out = mdr[0];
mem[31][0] = DFFEA(mem[31][0]_lut_out, clock, reset, , A1L959, , );

--A1L069Q is mem[31][0]~1329
--operation mode is normal

A1L069Q = mem[31][0];


--A1L3101 is Mux~2812
--operation mode is normal

A1L3101 = mem_addr[3] & (A1L2101 & (mem[31][0]) # !A1L2101 & mem[27][0]) # !mem_addr[3] & (A1L2101);