cpu.fit.eqn

这是接上面程序

--A1L899 is Mux~2794 at LC6_C51
--operation mode is normal

A1L899 = !add_r[2] & !add_r[3] & add_r[0] & add_r[1];

--A1L3731 is Mux~3192 at LC6_C51
--operation mode is normal

A1L3731 = !add_r[2] & !add_r[3] & add_r[0] & add_r[1];


--A1L421 is add_r~485 at LC7_C38
--operation mode is normal

A1L421 = !A1L299 & !A1L899 & A1L099 & A1L799;

--A1L821 is add_r~497 at LC7_C38
--operation mode is normal

A1L821 = !A1L299 & !A1L899 & A1L099 & A1L799;


--z_flag is z_flag at LC1_C47
--operation mode is normal

z_flag_lut_out = A1L8671;
z_flag = DFFEA(z_flag_lut_out, GLOBAL(clock), reset, , , , );

--A1L0381Q is z_flag~2 at LC1_C47
--operation mode is normal

A1L0381Q = z_flag;


--A1L521 is add_r~486 at LC3_C38
--operation mode is normal

A1L521 = !A1L199 & !z_flag & A1L421 # !A1L099;

--A1L921 is add_r~498 at LC3_C38
--operation mode is normal

A1L921 = !A1L199 & !z_flag & A1L421 # !A1L099;


--A1L621 is add_r~488 at LC8_C38
--operation mode is normal

A1L621 = A1L199 # A1L421 & z_flag;

--A1L031 is add_r~499 at LC8_C38
--operation mode is normal

A1L031 = A1L199 # A1L421 & z_flag;


--A1L721 is add_r~490 at LC2_C38
--operation mode is normal

A1L721 = A1L299 $ (A1L199 # !A1L421);

--A1L131 is add_r~500 at LC2_C38
--operation mode is normal

A1L131 = A1L299 $ (A1L199 # !A1L421);


--A1L999 is Mux~2795 at LC2_C51
--operation mode is normal

A1L999 = !add_r[0] & !add_r[3] & add_r[2] & add_r[1];

--A1L4731 is Mux~3193 at LC2_C51
--operation mode is normal

A1L4731 = !add_r[0] & !add_r[3] & add_r[2] & add_r[1];


--A1L0001 is Mux~2796 at LC4_C34
--operation mode is normal

A1L0001 = !add_r[3] & !add_r[1] & !add_r[0] & !add_r[2];

--A1L5731 is Mux~3194 at LC4_C34
--operation mode is normal

A1L5731 = !add_r[3] & !add_r[1] & !add_r[0] & !add_r[2];


--A1L1001 is Mux~2797 at LC2_C34
--operation mode is normal

A1L1001 = !add_r[1] & !add_r[2] & add_r[3] & add_r[0];

--A1L6731 is Mux~3195 at LC2_C34
--operation mode is normal

A1L6731 = !add_r[1] & !add_r[2] & add_r[3] & add_r[0];


--A1L2001 is Mux~2798 at LC5_C51
--operation mode is normal

A1L2001 = !add_r[2] & !add_r[0] & !add_r[3] & add_r[1];

--A1L7731 is Mux~3196 at LC5_C51
--operation mode is normal

A1L7731 = !add_r[2] & !add_r[0] & !add_r[3] & add_r[1];


--A1L3001 is Mux~2799 at LC1_C39
--operation mode is normal

A1L3001 = !add_r[3] & !add_r[1] & !add_r[0] & add_r[2];

--A1L8731 is Mux~3197 at LC1_C39
--operation mode is normal

A1L8731 = !add_r[3] & !add_r[1] & !add_r[0] & add_r[2];


--mdr[5] is mdr[5] at LC2_J40
--operation mode is normal

mdr[5]_lut_out = A1L223 # A1L699 & A1L1001 & A1L93;
mdr[5] = DFFEA(mdr[5]_lut_out, GLOBAL(clock), reset, , , , );

--A1L792Q is mdr[5]~2381 at LC2_J40
--operation mode is normal

A1L792Q = mdr[5];


--instr_reg[5] is instr_reg[5] at LC3_C49
--operation mode is normal

instr_reg[5]_lut_out = A1L2001 & (mdr[5]) # !A1L2001 & instr_reg[5];
instr_reg[5] = DFFEA(instr_reg[5]_lut_out, GLOBAL(clock), reset, , , , );

--A1L142Q is instr_reg[5]~360 at LC3_C49
--operation mode is normal

A1L142Q = instr_reg[5];


--mdr[6] is mdr[6] at LC1_L45
--operation mode is normal

mdr[6]_lut_out = A1L523 # A1L699 & A1L1001 & A1L24;
mdr[6] = DFFEA(mdr[6]_lut_out, GLOBAL(clock), reset, , , , );

--A1L992Q is mdr[6]~2382 at LC1_L45
--operation mode is normal

A1L992Q = mdr[6];


--instr_reg[6] is instr_reg[6] at LC4_C33
--operation mode is normal

instr_reg[6]_lut_out = A1L2001 & (mdr[6]) # !A1L2001 & instr_reg[6];
instr_reg[6] = DFFEA(instr_reg[6]_lut_out, GLOBAL(clock), reset, , , , );

--A1L342Q is instr_reg[6]~361 at LC4_C33
--operation mode is normal

A1L342Q = instr_reg[6];


--mdr[7] is mdr[7] at LC1_L48
--operation mode is normal

mdr[7]_lut_out = A1L823 # A1L699 & A1L1001 & A1L54;
mdr[7] = DFFEA(mdr[7]_lut_out, GLOBAL(clock), reset, , , , );

--A1L103Q is mdr[7]~2383 at LC1_L48
--operation mode is normal

A1L103Q = mdr[7];


--instr_reg[7] is instr_reg[7] at LC3_C39
--operation mode is normal

instr_reg[7]_lut_out = A1L2001 & (mdr[7]) # !A1L2001 & instr_reg[7];
instr_reg[7] = DFFEA(instr_reg[7]_lut_out, GLOBAL(clock), reset, , , , );

--A1L542Q is instr_reg[7]~362 at LC3_C39
--operation mode is normal

A1L542Q = instr_reg[7];


--mdr_out[0] is mdr_out[0] at LC5_C50
--operation mode is normal

mdr_out[0]_lut_out = A1L233;
mdr_out[0] = DFFEA(mdr_out[0]_lut_out, GLOBAL(clock), , , reset, , );

--A1L403Q is mdr_out[0]~40 at LC5_C50
--operation mode is normal

A1L403Q = mdr_out[0];


--mar_out[0] is mar_out[0] at LC6_C50
--operation mode is normal

mar_out[0]_lut_out = A1L699 & mar[0] # !A1L699 & (A1L1081);
mar_out[0] = DFFEA(mar_out[0]_lut_out, GLOBAL(clock), , , reset, , );

--A1L672Q is mar_out[0]~35 at LC6_C50
--operation mode is normal

A1L672Q = mar_out[0];


--A1L4001 is Mux~2800 at LC4_C50
--operation mode is normal

A1L4001 = mode[0] & (mdr_out[0]) # !mode[0] & mar_out[0];

--A1L9731 is Mux~3198 at LC4_C50
--operation mode is normal

A1L9731 = mode[0] & (mdr_out[0]) # !mode[0] & mar_out[0];


--G1_q[0] is lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[0] at LC2_C12
--operation mode is clrb_cntr

G1_q[0]_lut_out = ((A1L0001 $ G1_q[0] & A1L391) # (mdr[0] & !A1L391)) & VCC;
G1_q[0] = DFFEA(G1_q[0]_lut_out, GLOBAL(clock), reset, , , , );

--G1L31Q is lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~0 at LC2_C12
--operation mode is clrb_cntr

G1L31Q = G1_q[0];

--G1L3 is lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT at LC2_C12
--operation mode is clrb_cntr

G1L3 = CARRY(G1_q[0]);


--acc_out[0] is acc_out[0] at LC2_C43
--operation mode is normal

acc_out[0]_lut_out = A1L64 # A1L74 & A1L071;
acc_out[0] = DFFEA(acc_out[0]_lut_out, GLOBAL(clock), , , reset, , );

--A1L22Q is acc_out[0]~72 at LC2_C43
--operation mode is normal

A1L22Q = acc_out[0];


--sysbus[0] is sysbus[0] at LC3_C50
--operation mode is normal

sysbus[0]_lut_out = A1L599 & (A1L233) # !A1L599 & A1L1081;
sysbus[0] = DFFEA(sysbus[0]_lut_out, GLOBAL(clock), reset, , , , );

--A1L4871Q is sysbus[0]~2665 at LC3_C50
--operation mode is normal

A1L4871Q = sysbus[0];


--A1L5001 is Mux~2801 at LC4_C43
--operation mode is normal

A1L5001 = mode[1] & (acc_out[0] # mode[0]) # !mode[1] & sysbus[0] & (!mode[0]);

--A1L0831 is Mux~3199 at LC4_C43
--operation mode is normal

A1L0831 = mode[1] & (acc_out[0] # mode[0]) # !mode[1] & sysbus[0] & (!mode[0]);


--IR_out[0] is IR_out[0] at LC1_C8
--operation mode is normal

IR_out[0]_lut_out = A1L2001 & mdr[0] # !A1L2001 & (instr_reg[0]);
IR_out[0] = DFFEA(IR_out[0]_lut_out, GLOBAL(clock), , , reset, , );

--A1L842Q is IR_out[0]~43 at LC1_C8
--operation mode is normal

A1L842Q = IR_out[0];


--A1L6001 is Mux~2802 at LC6_C43
--operation mode is normal

A1L6001 = A1L5001 & (IR_out[0] # !mode[0]) # !A1L5001 & (mode[0] & G1_q[0]);

--A1L1831 is Mux~3200 at LC6_C43
--operation mode is normal

A1L1831 = A1L5001 & (IR_out[0] # !mode[0]) # !A1L5001 & (mode[0] & G1_q[0]);


--A1L7001 is Mux~2803 at LC3_B43
--operation mode is normal

A1L7001 = mode[2] & (mode[1] # !A1L4001) # !mode[2] & !A1L6001;

--A1L2831 is Mux~3201 at LC3_B43
--operation mode is normal

A1L2831 = mode[2] & (mode[1] # !A1L4001) # !mode[2] & !A1L6001;

--A1L3831 is Mux~3202 at LC3_B43
--operation mode is normal

A1L3831 = mode[2] & (mode[1] # !A1L4001) # !mode[2] & !A1L6001;


--mem[22][0] is mem[22][0] at LC2_B43
--operation mode is normal

mem[22][0]_lut_out = mdr[0];
mem[22][0] = DFFEA(mem[22][0]_lut_out, GLOBAL(clock), reset, , A1L197, , );

--A1L297Q is mem[22][0]~1314 at LC2_B43
--operation mode is normal

A1L297Q = mem[22][0];


--mem[26][0] is mem[26][0] at LC2_B32
--operation mode is normal

mem[26][0]_lut_out = mdr[0];
mem[26][0] = DFFEA(mem[26][0]_lut_out, GLOBAL(clock), reset, , A1L768, , );

--A1L868Q is mem[26][0]~1315 at LC2_B32
--operation mode is normal

A1L868Q = mem[26][0];


--mem[18][0] is mem[18][0] at LC3_B32
--operation mode is normal

mem[18][0]_lut_out = mdr[0];
mem[18][0] = DFFEA(mem[18][0]_lut_out, GLOBAL(clock), reset, , A1L517, , );

--A1L617Q is mem[18][0]~1316 at LC3_B32
--operation mode is normal

A1L617Q = mem[18][0];


--A1L8001 is Mux~2804 at LC6_B32
--operation mode is normal

A1L8001 = mem_addr[3] & (mem[26][0] # mem_addr[2]) # !mem_addr[3] & mem[18][0] & (!mem_addr[2]);

--A1L4831 is Mux~3203 at LC6_B32
--operation mode is normal

A1L4831 = mem_addr[3] & (mem[26][0] # mem_addr[2]) # !mem_addr[3] & mem[18][0] & (!mem_addr[2]);


--mem[30][0] is mem[30][0] at LC5_B43
--operation mode is normal

mem[30][0]_lut_out = mdr[0];
mem[30][0] = DFFEA(mem[30][0]_lut_out, GLOBAL(clock), reset, , A1L349, , );

--A1L449Q is mem[30][0]~1317 at LC5_B43
--operation mode is normal

A1L449Q = mem[30][0];


--A1L9001 is Mux~2805 at LC6_B43
--operation mode is normal

A1L9001 = A1L8001 & (mem[30][0] # !mem_addr[2]) # !A1L8001 & (mem_addr[2] & mem[22][0]);

--A1L5831 is Mux~3204 at LC6_B43
--operation mode is normal

A1L5831 = A1L8001 & (mem[30][0] # !mem_addr[2]) # !A1L8001 & (mem_addr[2] & mem[22][0]);


--mem[25][0] is mem[25][0] at LC3_B33
--operation mode is normal

mem[25][0]_lut_out = mdr[0];
mem[25][0] = DFFEA(mem[25][0]_lut_out, GLOBAL(clock), reset, , A1L848, , );

--A1L948Q is mem[25][0]~1318 at LC3_B33
--operation mode is normal

A1L948Q = mem[25][0];


--mem[21][0] is mem[21][0] at LC4_B33
--operation mode is normal

mem[21][0]_lut_out = mdr[0];
mem[21][0] = DFFEA(mem[21][0]_lut_out, GLOBAL(clock), reset, , A1L277, , );

--A1L377Q is mem[21][0]~1319 at LC4_B33
--operation mode is normal

A1L377Q = mem[21][0];


--mem[17][0] is mem[17][0] at LC5_B33
--operation mode is normal

mem[17][0]_lut_out = mdr[0];
mem[17][0] = DFFEA(mem[17][0]_lut_out, GLOBAL(clock), reset, , A1L696, , );

--A1L796Q is mem[17][0]~1320 at LC5_B33
--operation mode is normal

A1L796Q = mem[17][0];


--A1L0101 is Mux~2806 at LC6_B33
--operation mode is normal

A1L0101 = mem_addr[2] & (mem[21][0] # mem_addr[3]) # !mem_addr[2] & mem[17][0] & (!mem_addr[3]);

--A1L6831 is Mux~3205 at LC6_B33
--operation mode is normal

A1L6831 = mem_addr[2] & (mem[21][0] # mem_addr[3]) # !mem_addr[2] & mem[17][0] & (!mem_addr[3]);


--mem[29][0] is mem[29][0] at LC7_B33
--operation mode is normal

mem[29][0]_lut_out = mdr[0];
mem[29][0] = DFFEA(mem[29][0]_lut_out, GLOBAL(clock), reset, , A1L429, , );

--A1L529Q is mem[29][0]~1321 at LC7_B33
--operation mode is normal

A1L529Q = mem[29][0];


--A1L1101 is Mux~2807 at LC2_B33
--operation mode is normal

A1L1101 = A1L0101 & (mem[29][0] # !mem_addr[3]) # !A1L0101 & (mem_addr[3] & mem[25][0]);

--A1L7831 is Mux~3206 at LC2_B33
--operation mode is normal

A1L7831 = A1L0101 & (mem[29][0] # !mem_addr[3]) # !A1L0101 & (mem_addr[3] & mem[25][0]);


--mem[20][0] is mem[20][0] at LC3_B34
--operation mode is normal

mem[20][0]_lut_out = mdr[0];
mem[20][0] = DFFEA(mem[20][0]_lut_out, GLOBAL(clock), reset, , A1L357, , );

--A1L457Q is mem[20][0]~1322 at LC3_B34
--operation mode is normal

A1L457Q = mem[20][0];


--mem[24][0] is mem[24][0] at LC4_B34
--operation mode is normal

mem[24][0]_lut_out = mdr[0];
mem[24][0] = DFFEA(mem[24][0]_lut_out, GLOBAL(clock), reset, , A1L928, , );

--A1L038Q is mem[24][0]~1323 at LC4_B34
--operation mode is normal

A1L038Q = mem[24][0];


--mem[16][0] is mem[16][0] at LC5_B34
--operation mode is normal

mem[16][0]_lut_out = mdr[0];
mem[16][0] = DFFEA(mem[16][0]_lut_out, GLOBAL(clock), reset, , A1L776, , );

--A1L876Q is mem[16][0]~1324 at LC5_B34
--operation mode is normal

A1L876Q = mem[16][0];


--A1L2101 is Mux~2808 at LC6_B34
--operation mode is normal

A1L2101 = mem_addr[3] & (mem[24][0] # mem_addr[2]) # !mem_addr[3] & mem[16][0] & (!mem_addr[2]);

--A1L8831 is Mux~3207 at LC6_B34
--operation mode is normal

A1L8831 = mem_addr[3] & (mem[24][0] # mem_addr[2]) # !mem_addr[3] & mem[16][0] & (!mem_addr[2]);


--mem[28][0] is mem[28][0] at LC7_B34
--operation mode is normal

mem[28][0]_lut_out = mdr[0];
mem[28][0] = DFFEA(mem[28][0]_lut_out, GLOBAL(clock), reset, , A1L509, , );

--A1L609Q is mem[28][0]~1325 at LC7_B34
--operation mode is normal

A1L609Q = mem[28][0];


--A1L3101 is Mux~2809 at LC2_B34
--operation mode is normal

A1L3101 = A1L2101 & (mem[28][0] # !mem_addr[2]) # !A1L2101 & (mem_addr[2] & mem[20][0]);

--A1L9831 is Mux~3208 at LC2_B34