cpu.map.eqn

说明：cpuyuanma1是硬布线控制器源代码

--A1L792Q is mem[0][2]~876
--operation mode is normal

A1L792Q = mem[0][2];


--A1L159 is Mux~1917
--operation mode is normal

A1L159 = mar[1] & (mar[0]) # !mar[1] & (mar[0] & !mem[1][2] # !mar[0] & (!mem[0][2]));

--A1L0131 is Mux~2312
--operation mode is normal

A1L0131 = mar[1] & (mar[0]) # !mar[1] & (mar[0] & !mem[1][2] # !mar[0] & (!mem[0][2]));


--mem[3][2] is mem[3][2]
--operation mode is normal

mem[3][2]_lut_out = !mdr[2];
mem[3][2] = DFFEA(mem[3][2]_lut_out, clock, reset, , A1L843, , );

--A1L453Q is mem[3][2]~877
--operation mode is normal

A1L453Q = mem[3][2];


--A1L259 is Mux~1918
--operation mode is normal

A1L259 = mar[1] & (A1L159 & (!mem[3][2]) # !A1L159 & !mem[2][2]) # !mar[1] & (A1L159);

--A1L1131 is Mux~2313
--operation mode is normal

A1L1131 = mar[1] & (A1L159 & (!mem[3][2]) # !A1L159 & !mem[2][2]) # !mar[1] & (A1L159);


--A1L359 is Mux~1919
--operation mode is normal

A1L359 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & A1L059 # !mar[2] & (A1L259));

--A1L2131 is Mux~2314
--operation mode is normal

A1L2131 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & A1L059 # !mar[2] & (A1L259));


--mem[13][2] is mem[13][2]
--operation mode is normal

mem[13][2]_lut_out = mdr[2];
mem[13][2] = DFFEA(mem[13][2]_lut_out, clock, reset, , A1L835, , );

--A1L445Q is mem[13][2]~878
--operation mode is normal

A1L445Q = mem[13][2];


--mem[14][2] is mem[14][2]
--operation mode is normal

mem[14][2]_lut_out = mdr[2];
mem[14][2] = DFFEA(mem[14][2]_lut_out, clock, reset, , A1L755, , );

--A1L365Q is mem[14][2]~879
--operation mode is normal

A1L365Q = mem[14][2];


--mem[12][2] is mem[12][2]
--operation mode is normal

mem[12][2]_lut_out = mdr[2];
mem[12][2] = DFFEA(mem[12][2]_lut_out, clock, reset, , A1L915, , );

--A1L525Q is mem[12][2]~880
--operation mode is normal

A1L525Q = mem[12][2];


--A1L459 is Mux~1920
--operation mode is normal

A1L459 = mar[0] & (mar[1]) # !mar[0] & (mar[1] & mem[14][2] # !mar[1] & (mem[12][2]));

--A1L3131 is Mux~2315
--operation mode is normal

A1L3131 = mar[0] & (mar[1]) # !mar[0] & (mar[1] & mem[14][2] # !mar[1] & (mem[12][2]));


--mem[15][2] is mem[15][2]
--operation mode is normal

mem[15][2]_lut_out = mdr[2];
mem[15][2] = DFFEA(mem[15][2]_lut_out, clock, reset, , A1L675, , );

--A1L285Q is mem[15][2]~881
--operation mode is normal

A1L285Q = mem[15][2];


--A1L559 is Mux~1921
--operation mode is normal

A1L559 = mar[0] & (A1L459 & (mem[15][2]) # !A1L459 & mem[13][2]) # !mar[0] & (A1L459);

--A1L4131 is Mux~2316
--operation mode is normal

A1L4131 = mar[0] & (A1L459 & (mem[15][2]) # !A1L459 & mem[13][2]) # !mar[0] & (A1L459);


--A1L659 is Mux~1922
--operation mode is normal

A1L659 = mar[3] & (A1L359 & (A1L559) # !A1L359 & A1L849) # !mar[3] & (A1L359);

--A1L5131 is Mux~2317
--operation mode is normal

A1L5131 = mar[3] & (A1L359 & (A1L559) # !A1L359 & A1L849) # !mar[3] & (A1L359);


--A1L442 is mdr~2407
--operation mode is normal

A1L442 = A1L632 & (A1L659 # A1L532 & mdr[2]) # !A1L632 & A1L532 & mdr[2];

--A1L172 is mdr~2445
--operation mode is normal

A1L172 = A1L632 & (A1L659 # A1L532 & mdr[2]) # !A1L632 & A1L532 & mdr[2];


--mem[22][2] is mem[22][2]
--operation mode is normal

mem[22][2]_lut_out = mdr[2];
mem[22][2] = DFFEA(mem[22][2]_lut_out, clock, reset, , A1L907, , );

--A1L517Q is mem[22][2]~882
--operation mode is normal

A1L517Q = mem[22][2];


--mem[26][2] is mem[26][2]
--operation mode is normal

mem[26][2]_lut_out = mdr[2];
mem[26][2] = DFFEA(mem[26][2]_lut_out, clock, reset, , A1L587, , );

--A1L197Q is mem[26][2]~883
--operation mode is normal

A1L197Q = mem[26][2];


--mem[18][2] is mem[18][2]
--operation mode is normal

mem[18][2]_lut_out = mdr[2];
mem[18][2] = DFFEA(mem[18][2]_lut_out, clock, reset, , A1L336, , );

--A1L936Q is mem[18][2]~884
--operation mode is normal

A1L936Q = mem[18][2];


--A1L759 is Mux~1923
--operation mode is normal

A1L759 = mar[2] & (mar[3]) # !mar[2] & (mar[3] & mem[26][2] # !mar[3] & (mem[18][2]));

--A1L6131 is Mux~2318
--operation mode is normal

A1L6131 = mar[2] & (mar[3]) # !mar[2] & (mar[3] & mem[26][2] # !mar[3] & (mem[18][2]));


--mem[30][2] is mem[30][2]
--operation mode is normal

mem[30][2]_lut_out = mdr[2];
mem[30][2] = DFFEA(mem[30][2]_lut_out, clock, reset, , A1L168, , );

--A1L768Q is mem[30][2]~885
--operation mode is normal

A1L768Q = mem[30][2];


--A1L859 is Mux~1924
--operation mode is normal

A1L859 = mar[2] & (A1L759 & (mem[30][2]) # !A1L759 & mem[22][2]) # !mar[2] & (A1L759);

--A1L7131 is Mux~2319
--operation mode is normal

A1L7131 = mar[2] & (A1L759 & (mem[30][2]) # !A1L759 & mem[22][2]) # !mar[2] & (A1L759);


--mem[25][2] is mem[25][2]
--operation mode is normal

mem[25][2]_lut_out = mdr[2];
mem[25][2] = DFFEA(mem[25][2]_lut_out, clock, reset, , A1L667, , );

--A1L277Q is mem[25][2]~886
--operation mode is normal

A1L277Q = mem[25][2];


--mem[21][2] is mem[21][2]
--operation mode is normal

mem[21][2]_lut_out = mdr[2];
mem[21][2] = DFFEA(mem[21][2]_lut_out, clock, reset, , A1L096, , );

--A1L696Q is mem[21][2]~887
--operation mode is normal

A1L696Q = mem[21][2];


--mem[17][2] is mem[17][2]
--operation mode is normal

mem[17][2]_lut_out = mdr[2];
mem[17][2] = DFFEA(mem[17][2]_lut_out, clock, reset, , A1L416, , );

--A1L026Q is mem[17][2]~888
--operation mode is normal

A1L026Q = mem[17][2];


--A1L959 is Mux~1925
--operation mode is normal

A1L959 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & mem[21][2] # !mar[2] & (mem[17][2]));

--A1L8131 is Mux~2320
--operation mode is normal

A1L8131 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & mem[21][2] # !mar[2] & (mem[17][2]));


--mem[29][2] is mem[29][2]
--operation mode is normal

mem[29][2]_lut_out = mdr[2];
mem[29][2] = DFFEA(mem[29][2]_lut_out, clock, reset, , A1L248, , );

--A1L848Q is mem[29][2]~889
--operation mode is normal

A1L848Q = mem[29][2];


--A1L069 is Mux~1926
--operation mode is normal

A1L069 = mar[3] & (A1L959 & (mem[29][2]) # !A1L959 & mem[25][2]) # !mar[3] & (A1L959);

--A1L9131 is Mux~2321
--operation mode is normal

A1L9131 = mar[3] & (A1L959 & (mem[29][2]) # !A1L959 & mem[25][2]) # !mar[3] & (A1L959);


--mem[20][2] is mem[20][2]
--operation mode is normal

mem[20][2]_lut_out = mdr[2];
mem[20][2] = DFFEA(mem[20][2]_lut_out, clock, reset, , A1L176, , );

--A1L776Q is mem[20][2]~890
--operation mode is normal

A1L776Q = mem[20][2];


--mem[24][2] is mem[24][2]
--operation mode is normal

mem[24][2]_lut_out = mdr[2];
mem[24][2] = DFFEA(mem[24][2]_lut_out, clock, reset, , A1L747, , );

--A1L357Q is mem[24][2]~891
--operation mode is normal

A1L357Q = mem[24][2];


--mem[16][2] is mem[16][2]
--operation mode is normal

mem[16][2]_lut_out = mdr[2];
mem[16][2] = DFFEA(mem[16][2]_lut_out, clock, reset, , A1L595, , );

--A1L106Q is mem[16][2]~892
--operation mode is normal

A1L106Q = mem[16][2];


--A1L169 is Mux~1927
--operation mode is normal

A1L169 = mar[2] & (mar[3]) # !mar[2] & (mar[3] & mem[24][2] # !mar[3] & (mem[16][2]));

--A1L0231 is Mux~2322
--operation mode is normal

A1L0231 = mar[2] & (mar[3]) # !mar[2] & (mar[3] & mem[24][2] # !mar[3] & (mem[16][2]));


--mem[28][2] is mem[28][2]
--operation mode is normal

mem[28][2]_lut_out = mdr[2];
mem[28][2] = DFFEA(mem[28][2]_lut_out, clock, reset, , A1L328, , );

--A1L928Q is mem[28][2]~893
--operation mode is normal

A1L928Q = mem[28][2];


--A1L269 is Mux~1928
--operation mode is normal

A1L269 = mar[2] & (A1L169 & (mem[28][2]) # !A1L169 & mem[20][2]) # !mar[2] & (A1L169);

--A1L1231 is Mux~2323
--operation mode is normal

A1L1231 = mar[2] & (A1L169 & (mem[28][2]) # !A1L169 & mem[20][2]) # !mar[2] & (A1L169);


--A1L369 is Mux~1929
--operation mode is normal

A1L369 = mar[1] & (mar[0]) # !mar[1] & (mar[0] & A1L069 # !mar[0] & (A1L269));

--A1L2231 is Mux~2324
--operation mode is normal

A1L2231 = mar[1] & (mar[0]) # !mar[1] & (mar[0] & A1L069 # !mar[0] & (A1L269));


--mem[27][2] is mem[27][2]
--operation mode is normal

mem[27][2]_lut_out = mdr[2];
mem[27][2] = DFFEA(mem[27][2]_lut_out, clock, reset, , A1L408, , );

--A1L018Q is mem[27][2]~894
--operation mode is normal

A1L018Q = mem[27][2];


--mem[23][2] is mem[23][2]
--operation mode is normal

mem[23][2]_lut_out = mdr[2];
mem[23][2] = DFFEA(mem[23][2]_lut_out, clock, reset, , A1L827, , );

--A1L437Q is mem[23][2]~895
--operation mode is normal

A1L437Q = mem[23][2];


--mem[19][2] is mem[19][2]
--operation mode is normal

mem[19][2]_lut_out = mdr[2];
mem[19][2] = DFFEA(mem[19][2]_lut_out, clock, reset, , A1L256, , );

--A1L856Q is mem[19][2]~896
--operation mode is normal

A1L856Q = mem[19][2];


--A1L469 is Mux~1930
--operation mode is normal

A1L469 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & mem[23][2] # !mar[2] & (mem[19][2]));

--A1L3231 is Mux~2325
--operation mode is normal

A1L3231 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & mem[23][2] # !mar[2] & (mem[19][2]));


--mem[31][2] is mem[31][2]
--operation mode is normal

mem[31][2]_lut_out = mdr[2];
mem[31][2] = DFFEA(mem[31][2]_lut_out, clock, reset, , A1L088, , );

--A1L688Q is mem[31][2]~897
--operation mode is normal

A1L688Q = mem[31][2];


--A1L569 is Mux~1931
--operation mode is normal

A1L569 = mar[3] & (A1L469 & (mem[31][2]) # !A1L469 & mem[27][2]) # !mar[3] & (A1L469);

--A1L4231 is Mux~2326
--operation mode is normal

A1L4231 = mar[3] & (A1L469 & (mem[31][2]) # !A1L469 & mem[27][2]) # !mar[3] & (A1L469);


--A1L669 is Mux~1932
--operation mode is normal

A1L669 = mar[1] & (A1L369 & (A1L569) # !A1L369 & A1L859) # !mar[1] & (A1L369);

--A1L5231 is Mux~2327
--operation mode is normal

A1L5231 = mar[1] & (A1L369 & (A1L569) # !A1L369 & A1L859) # !mar[1] & (A1L369);


--A1L542 is mdr~2408
--operation mode is normal

A1L542 = A1L442 # A1L832 & A1L669;

--A1L272 is mdr~2446
--operation mode is normal

A1L272 = A1L442 # A1L832 & A1L669;


--acc[2] is acc[2]
--operation mode is normal

acc[2]_lut_out = A1L44 # present_state.s8 & A1L54;
acc[2] = DFFEA(acc[2]_lut_out, clock, reset, , , , );

--A1L9Q is acc[2]~1819
--operation mode is normal

A1L9Q = acc[2];


--A1L44 is acc~1778
--operation mode is normal

A1L44 = !A1L601 & (present_state.s7 & mdr[2] # !present_state.s7 & (acc[2]));

--A1L57 is acc~1820
--operation mode is normal

A1L57 = !A1L601 & (present_state.s7 & mdr[2] # !present_state.s7 & (acc[2]));


--F3_cs_buffer[2] is lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

F3_cs_buffer[2] = mdr[2] $ A1L46 $ F3_cout[1];

--F3L51 is lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~138
--operation mode is arithmetic

F3L51 = mdr[2] $ A1L46 $ F3_cout[1];

--F3_cout[2] is lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

F3_cout[2] = CARRY(mdr[2] & (A1L46 # F3_cout[1]) # !mdr[2] & A1L46 & F3_cout[1]);


--F6_cs_buffer[3] is lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

F6_cs_buffer[3] = mdr[2] $ A1L46 $ F6_cout[2];

--F6L51 is lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~138
--operation mode is arithmetic

F6L51 = mdr[2] $ A1L46 $ F6_cout[2];

--F6_cout[3] is lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

F6_cout[3] = CARRY(mdr[2] & A1L46 & F6_cout[2] # !mdr[2] & (A1L46 # F6_cout[2]));


--A1L54 is acc~1779
--operation mode is normal

A1L54 = A1L301 & F3_cs_buffer[2] # !A1L301 & (A1L701 & !F6_cs_buffer[3]);

--A1L67 is acc~1821
--operation mode is normal

A1L67 = A1L301 & F3_cs_buffer[2] # !A1L301 & (A1L701 & !F6_cs_buffer[3]);


--A1L64 is acc~1780
--operation mode is normal

A1L64 = A1L44 # present_state.s8 & A1L54;

--A1L77 is acc~1822
--operation mode is normal

A1L77 = A1L44 # present_state.s8 & A1L54;


--instr_reg[2] is instr_reg[2]
--operation mode is normal

instr_reg[2]_lut_out = present_state.s2 & mdr[2] # !present_state.s2 & (instr_reg[2]);
instr_reg[2] = DFFEA(instr_reg[2]_lut_out, clock, reset, , , , );

--A1L151Q is instr_reg[2]~49
--operation mode is normal

A1L151Q = instr_reg[2];


--A1L6371 is sysbus~2736
--operation mode is normal

A1L6371 = present_state.s3 & (present_state.s2 & mdr[2] # !present_state.s2 & (instr_reg[2]));

--A1L5571 is sysbus~2769
--operation mode is normal

A1L5571 = present_state.s3 & (present_state.s2 & mdr[2] # !present_state.s2 & (instr_reg[2]));


--G1_q[2] is lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

G1_q[2]_lut_out = ((G1_q[2] $ (!present_state.s0 & G1L5) & A1L4761) # (mdr[2] & !A1L4761)) & VCC;
G1_q[2]