cpu.map.eqn

说明：cpuyuanma1是硬布线控制器源代码

--operation mode is normal

mem[13][0]_lut_out = mdr[0];
mem[13][0] = DFFEA(mem[13][0]_lut_out, clock, reset, , A1L835, , );

--A1L935Q is mem[13][0]~814
--operation mode is normal

A1L935Q = mem[13][0];


--mem[14][0] is mem[14][0]
--operation mode is normal

mem[14][0]_lut_out = mdr[0];
mem[14][0] = DFFEA(mem[14][0]_lut_out, clock, reset, , A1L755, , );

--A1L855Q is mem[14][0]~815
--operation mode is normal

A1L855Q = mem[14][0];


--mem[12][0] is mem[12][0]
--operation mode is normal

mem[12][0]_lut_out = mdr[0];
mem[12][0] = DFFEA(mem[12][0]_lut_out, clock, reset, , A1L915, , );

--A1L025Q is mem[12][0]~816
--operation mode is normal

A1L025Q = mem[12][0];


--A1L419 is Mux~1880
--operation mode is normal

A1L419 = mar[0] & (mar[1]) # !mar[0] & (mar[1] & mem[14][0] # !mar[1] & (mem[12][0]));

--A1L3721 is Mux~2275
--operation mode is normal

A1L3721 = mar[0] & (mar[1]) # !mar[0] & (mar[1] & mem[14][0] # !mar[1] & (mem[12][0]));


--mem[15][0] is mem[15][0]
--operation mode is normal

mem[15][0]_lut_out = mdr[0];
mem[15][0] = DFFEA(mem[15][0]_lut_out, clock, reset, , A1L675, , );

--A1L775Q is mem[15][0]~817
--operation mode is normal

A1L775Q = mem[15][0];


--A1L519 is Mux~1881
--operation mode is normal

A1L519 = mar[0] & (A1L419 & (mem[15][0]) # !A1L419 & mem[13][0]) # !mar[0] & (A1L419);

--A1L4721 is Mux~2276
--operation mode is normal

A1L4721 = mar[0] & (A1L419 & (mem[15][0]) # !A1L419 & mem[13][0]) # !mar[0] & (A1L419);


--A1L619 is Mux~1882
--operation mode is normal

A1L619 = mar[3] & (A1L319 & (A1L519) # !A1L319 & A1L809) # !mar[3] & (A1L319);

--A1L5721 is Mux~2277
--operation mode is normal

A1L5721 = mar[3] & (A1L319 & (A1L519) # !A1L319 & A1L809) # !mar[3] & (A1L319);


--mdr[0] is mdr[0]
--operation mode is normal

mdr[0]_lut_out = A1L932 # A1L2371 & present_state.s4 & !A1L9271;
mdr[0] = DFFEA(mdr[0]_lut_out, clock, reset, , , , );

--A1L202Q is mdr[0]~2433
--operation mode is normal

A1L202Q = mdr[0];


--A1L2961 is reduce_or~65
--operation mode is normal

A1L2961 = present_state.s1 # present_state.s6;

--A1L9961 is reduce_or~72
--operation mode is normal

A1L9961 = present_state.s1 # present_state.s6;


--present_state.s0 is present_state.s0
--operation mode is normal

present_state.s0_lut_out = !present_state.s8 & !present_state.s10 & (A1L9861);
present_state.s0 = DFFEA(present_state.s0_lut_out, clock, reset, , , , );

--A1L6561Q is present_state.s0~14
--operation mode is normal

A1L6561Q = present_state.s0;


--A1L532 is mdr~2398
--operation mode is normal

A1L532 = present_state.s3 # !A1L2961 & !present_state.s4 # !present_state.s0;

--A1L262 is mdr~2434
--operation mode is normal

A1L262 = present_state.s3 # !A1L2961 & !present_state.s4 # !present_state.s0;


--mar[4] is mar[4]
--operation mode is normal

mar[4]_lut_out = present_state.s0 & (present_state.s3 & A1L4471 # !present_state.s3 & (mar[4])) # !present_state.s0 & A1L4471;
mar[4] = DFFEA(mar[4]_lut_out, clock, reset, , , , );

--A1L881Q is mar[4]~799
--operation mode is normal

A1L881Q = mar[4];


--A1L9271 is sysbus~2727
--operation mode is normal

A1L9271 = present_state.s3 # !present_state.s0;

--A1L8471 is sysbus~2762
--operation mode is normal

A1L8471 = present_state.s3 # !present_state.s0;


--A1L632 is mdr~2399
--operation mode is normal

A1L632 = !mar[4] & A1L2961 & !present_state.s4 & !A1L9271;

--A1L362 is mdr~2435
--operation mode is normal

A1L362 = !mar[4] & A1L2961 & !present_state.s4 & !A1L9271;


--A1L732 is mdr~2400
--operation mode is normal

A1L732 = A1L619 & (A1L632 # mdr[0] & A1L532) # !A1L619 & mdr[0] & A1L532;

--A1L462 is mdr~2436
--operation mode is normal

A1L462 = A1L619 & (A1L632 # mdr[0] & A1L532) # !A1L619 & mdr[0] & A1L532;


--mem[22][0] is mem[22][0]
--operation mode is normal

mem[22][0]_lut_out = mdr[0];
mem[22][0] = DFFEA(mem[22][0]_lut_out, clock, reset, , A1L907, , );

--A1L017Q is mem[22][0]~818
--operation mode is normal

A1L017Q = mem[22][0];


--mem[26][0] is mem[26][0]
--operation mode is normal

mem[26][0]_lut_out = mdr[0];
mem[26][0] = DFFEA(mem[26][0]_lut_out, clock, reset, , A1L587, , );

--A1L687Q is mem[26][0]~819
--operation mode is normal

A1L687Q = mem[26][0];


--mem[18][0] is mem[18][0]
--operation mode is normal

mem[18][0]_lut_out = mdr[0];
mem[18][0] = DFFEA(mem[18][0]_lut_out, clock, reset, , A1L336, , );

--A1L436Q is mem[18][0]~820
--operation mode is normal

A1L436Q = mem[18][0];


--A1L719 is Mux~1883
--operation mode is normal

A1L719 = mar[2] & (mar[3]) # !mar[2] & (mar[3] & mem[26][0] # !mar[3] & (mem[18][0]));

--A1L6721 is Mux~2278
--operation mode is normal

A1L6721 = mar[2] & (mar[3]) # !mar[2] & (mar[3] & mem[26][0] # !mar[3] & (mem[18][0]));


--mem[30][0] is mem[30][0]
--operation mode is normal

mem[30][0]_lut_out = mdr[0];
mem[30][0] = DFFEA(mem[30][0]_lut_out, clock, reset, , A1L168, , );

--A1L268Q is mem[30][0]~821
--operation mode is normal

A1L268Q = mem[30][0];


--A1L819 is Mux~1884
--operation mode is normal

A1L819 = mar[2] & (A1L719 & (mem[30][0]) # !A1L719 & mem[22][0]) # !mar[2] & (A1L719);

--A1L7721 is Mux~2279
--operation mode is normal

A1L7721 = mar[2] & (A1L719 & (mem[30][0]) # !A1L719 & mem[22][0]) # !mar[2] & (A1L719);


--mem[25][0] is mem[25][0]
--operation mode is normal

mem[25][0]_lut_out = mdr[0];
mem[25][0] = DFFEA(mem[25][0]_lut_out, clock, reset, , A1L667, , );

--A1L767Q is mem[25][0]~822
--operation mode is normal

A1L767Q = mem[25][0];


--mem[21][0] is mem[21][0]
--operation mode is normal

mem[21][0]_lut_out = mdr[0];
mem[21][0] = DFFEA(mem[21][0]_lut_out, clock, reset, , A1L096, , );

--A1L196Q is mem[21][0]~823
--operation mode is normal

A1L196Q = mem[21][0];


--mem[17][0] is mem[17][0]
--operation mode is normal

mem[17][0]_lut_out = mdr[0];
mem[17][0] = DFFEA(mem[17][0]_lut_out, clock, reset, , A1L416, , );

--A1L516Q is mem[17][0]~824
--operation mode is normal

A1L516Q = mem[17][0];


--A1L919 is Mux~1885
--operation mode is normal

A1L919 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & mem[21][0] # !mar[2] & (mem[17][0]));

--A1L8721 is Mux~2280
--operation mode is normal

A1L8721 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & mem[21][0] # !mar[2] & (mem[17][0]));


--mem[29][0] is mem[29][0]
--operation mode is normal

mem[29][0]_lut_out = mdr[0];
mem[29][0] = DFFEA(mem[29][0]_lut_out, clock, reset, , A1L248, , );

--A1L348Q is mem[29][0]~825
--operation mode is normal

A1L348Q = mem[29][0];


--A1L029 is Mux~1886
--operation mode is normal

A1L029 = mar[3] & (A1L919 & (mem[29][0]) # !A1L919 & mem[25][0]) # !mar[3] & (A1L919);

--A1L9721 is Mux~2281
--operation mode is normal

A1L9721 = mar[3] & (A1L919 & (mem[29][0]) # !A1L919 & mem[25][0]) # !mar[3] & (A1L919);


--mem[20][0] is mem[20][0]
--operation mode is normal

mem[20][0]_lut_out = mdr[0];
mem[20][0] = DFFEA(mem[20][0]_lut_out, clock, reset, , A1L176, , );

--A1L276Q is mem[20][0]~826
--operation mode is normal

A1L276Q = mem[20][0];


--mem[24][0] is mem[24][0]
--operation mode is normal

mem[24][0]_lut_out = mdr[0];
mem[24][0] = DFFEA(mem[24][0]_lut_out, clock, reset, , A1L747, , );

--A1L847Q is mem[24][0]~827
--operation mode is normal

A1L847Q = mem[24][0];


--mem[16][0] is mem[16][0]
--operation mode is normal

mem[16][0]_lut_out = mdr[0];
mem[16][0] = DFFEA(mem[16][0]_lut_out, clock, reset, , A1L595, , );

--A1L695Q is mem[16][0]~828
--operation mode is normal

A1L695Q = mem[16][0];


--A1L129 is Mux~1887
--operation mode is normal

A1L129 = mar[2] & (mar[3]) # !mar[2] & (mar[3] & mem[24][0] # !mar[3] & (mem[16][0]));

--A1L0821 is Mux~2282
--operation mode is normal

A1L0821 = mar[2] & (mar[3]) # !mar[2] & (mar[3] & mem[24][0] # !mar[3] & (mem[16][0]));


--mem[28][0] is mem[28][0]
--operation mode is normal

mem[28][0]_lut_out = mdr[0];
mem[28][0] = DFFEA(mem[28][0]_lut_out, clock, reset, , A1L328, , );

--A1L428Q is mem[28][0]~829
--operation mode is normal

A1L428Q = mem[28][0];


--A1L229 is Mux~1888
--operation mode is normal

A1L229 = mar[2] & (A1L129 & (mem[28][0]) # !A1L129 & mem[20][0]) # !mar[2] & (A1L129);

--A1L1821 is Mux~2283
--operation mode is normal

A1L1821 = mar[2] & (A1L129 & (mem[28][0]) # !A1L129 & mem[20][0]) # !mar[2] & (A1L129);


--A1L329 is Mux~1889
--operation mode is normal

A1L329 = mar[1] & (mar[0]) # !mar[1] & (mar[0] & A1L029 # !mar[0] & (A1L229));

--A1L2821 is Mux~2284
--operation mode is normal

A1L2821 = mar[1] & (mar[0]) # !mar[1] & (mar[0] & A1L029 # !mar[0] & (A1L229));


--mem[27][0] is mem[27][0]
--operation mode is normal

mem[27][0]_lut_out = mdr[0];
mem[27][0] = DFFEA(mem[27][0]_lut_out, clock, reset, , A1L408, , );

--A1L508Q is mem[27][0]~830
--operation mode is normal

A1L508Q = mem[27][0];


--mem[23][0] is mem[23][0]
--operation mode is normal

mem[23][0]_lut_out = mdr[0];
mem[23][0] = DFFEA(mem[23][0]_lut_out, clock, reset, , A1L827, , );

--A1L927Q is mem[23][0]~831
--operation mode is normal

A1L927Q = mem[23][0];


--mem[19][0] is mem[19][0]
--operation mode is normal

mem[19][0]_lut_out = mdr[0];
mem[19][0] = DFFEA(mem[19][0]_lut_out, clock, reset, , A1L256, , );

--A1L356Q is mem[19][0]~832
--operation mode is normal

A1L356Q = mem[19][0];


--A1L429 is Mux~1890
--operation mode is normal

A1L429 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & mem[23][0] # !mar[2] & (mem[19][0]));

--A1L3821 is Mux~2285
--operation mode is normal

A1L3821 = mar[3] & (mar[2]) # !mar[3] & (mar[2] & mem[23][0] # !mar[2] & (mem[19][0]));


--mem[31][0] is mem[31][0]
--operation mode is normal

mem[31][0]_lut_out = mdr[0];
mem[31][0] = DFFEA(mem[31][0]_lut_out, clock, reset, , A1L088, , );

--A1L188Q is mem[31][0]~833
--operation mode is normal

A1L188Q = mem[31][0];


--A1L529 is Mux~1891
--operation mode is normal

A1L529 = mar[3] & (A1L429 & (mem[31][0]) # !A1L429 & mem[27][0]) # !mar[3] & (A1L429);

--A1L4821 is Mux~2286
--operation mode is normal

A1L4821 = mar[3] & (A1L429 & (mem[31][0]) # !A1L429 & mem[27][0]) # !mar[3] & (A1L429);


--A1L629 is Mux~1892
--operation mode is normal

A1L629 = mar[1] & (A1L329 & (A1L529) # !A1L329 & A1L819) # !mar[1] & (A1L329);

--A1L5821 is Mux~2287
--operation mode is normal

A1L5821 = mar[1] & (A1L329 & (A1L529) # !A1L329 & A1L819) # !mar[1] & (A1L329);


--A1L832 is mdr~2401
--operation mode is normal

A1L832 = mar[4] & A1L2961 & !present_state.s4 & !A1L9271;

--A1L562 is mdr~2437
--operation mode is normal

A1L562 = mar[4] & A1L2961 & !present_state.s4 & !A1L9271;


--A1L932 is mdr~2402
--operation mode is normal

A1L932 = A1L732 # A1L629 & A1L832;

--A1L662 is mdr~2438
--operation mode is normal

A1L662 = A1L732 # A1L629 & A1L832;


--acc[0] is acc[0]
--operation mode is normal

acc[0]_lut_out = A1L83 # present_state.s8 & A1L93;
acc[0] = DFFEA(acc[0]_lut_out, clock, reset, , , , );

--A1L5Q is acc[0]~1811
--operation mode is normal

A1L5Q = acc[0];


--op[1] is op[1]
--operation mode is normal

op[1]_lut_out = present_state.s2 & (mdr[6]) # !present_state.s2 & instr_reg[6];
op[1] = DFFEA(op[1]_lut_out, clock, , , reset, , );

--A1L7361Q is op[1]~121
--operation mode is normal

A1L7361Q = op[1];


--op[2] is op[2]
--operation mode is normal

op[2]_lut_out = present_state.s2 & (mdr[7]) # !present_state.s2 & instr_reg[7];
op[2] = DFFEA(op[2]_lut_out, clock, , , reset, , );

--A1L9361Q is op[2]~122
--operation mode is normal

A1L9361Q = op[2];


--A1L601 is ALU_sub~29
--operation mode is normal

A1L601 = present_state.s8 & op[1] & (!op[2]);

--A1L801 is ALU_sub~31
--operation mode is normal

A1L801 = present_state.s8 & op[1] & (!op[2]);


--A1L83 is acc~1772
--operation mode is normal

A1L83 = !A1L601 & (present_state.s7 & mdr[0] # !present_state.s7 & (acc[0]));

--A1L96 is acc~1812
--operation mode is normal

A1L96 = !A1L601 & (present_state.s7 & mdr[0] # !present_state.s7 & (acc[0]));


--F3_cs_buffer[0] is lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

F3_cs_buffer[0] = mdr[0] $ A1L26;

--F3L11 is lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~136
--operation mode is arithmetic

F3L11 = mdr[0] $ A1L26;

--F3_cout[0] is lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic