cpu.hier_info

说明：cpuyuanma1是硬布线控制器源代码

reset => mem[2][4].ACLR
reset => mem[2][3].ACLR
reset => mem[2][2].PRESET
reset => mem[2][1].PRESET
reset => mem[2][0].ACLR
reset => mem[3][7].PRESET
reset => mem[3][6].ACLR
reset => mem[3][5].ACLR
reset => mem[3][4].ACLR
reset => mem[3][3].ACLR
reset => mem[3][2].PRESET
reset => mem[3][1].PRESET
reset => mem[3][0].PRESET
reset => mem[4][7].ACLR
reset => mem[4][6].ACLR
reset => mem[4][5].ACLR
reset => mem[4][4].ACLR
reset => mem[4][3].ACLR
reset => mem[4][2].ACLR
reset => mem[4][1].PRESET
reset => mem[4][0].ACLR
reset => mem[5][7].ACLR
reset => mem[5][6].ACLR
reset => mem[5][5].ACLR
reset => mem[5][4].ACLR
reset => mem[5][3].ACLR
reset => mem[5][2].ACLR
reset => mem[5][1].PRESET
reset => mem[5][0].PRESET
reset => mem[6][7].ACLR
reset => mem[6][6].ACLR
reset => mem[6][5].ACLR
reset => mem[6][4].ACLR
reset => mem[6][3].ACLR
reset => mem[6][2].ACLR
reset => mem[6][1].ACLR
reset => mem[6][0].ACLR
reset => mem[7][7].ACLR
reset => mem[7][6].ACLR
reset => mem[7][5].ACLR
reset => mem[7][4].ACLR
reset => mem[7][3].ACLR
reset => mem[7][2].ACLR
reset => mem[7][1].ACLR
reset => mem[7][0].ACLR
reset => mem[8][7].ACLR
reset => mem[8][6].ACLR
reset => mem[8][5].ACLR
reset => mem[8][4].ACLR
reset => mem[8][3].ACLR
reset => mem[8][2].ACLR
reset => mem[8][1].ACLR
reset => mem[8][0].ACLR
reset => mem[9][7].ACLR
reset => mem[9][6].ACLR
reset => mem[9][5].ACLR
reset => mem[9][4].ACLR
reset => mem[9][3].ACLR
reset => mem[9][2].ACLR
reset => mem[9][1].ACLR
reset => mem[9][0].ACLR
reset => mem[10][7].ACLR
reset => mem[10][6].ACLR
reset => mem[10][5].ACLR
reset => mem[10][4].ACLR
reset => mem[10][3].ACLR
reset => mem[10][2].ACLR
reset => mem[10][1].ACLR
reset => mem[10][0].ACLR
reset => mem[11][7].ACLR
reset => mem[11][6].ACLR
reset => mem[11][5].ACLR
reset => mem[11][4].ACLR
reset => mem[11][3].ACLR
reset => mem[11][2].ACLR
reset => mem[11][1].ACLR
reset => mem[11][0].ACLR
reset => mem[12][7].ACLR
reset => mem[12][6].ACLR
reset => mem[12][5].ACLR
reset => mem[12][4].ACLR
reset => mem[12][3].ACLR
reset => mem[12][2].ACLR
reset => mem[12][1].ACLR
reset => mem[12][0].ACLR
reset => mem[13][7].ACLR
reset => mem[13][6].ACLR
reset => mem[13][5].ACLR
reset => mem[13][4].ACLR
reset => mem[13][3].ACLR
reset => mem[13][2].ACLR
reset => mem[13][1].ACLR
reset => mem[13][0].ACLR
reset => mem[14][7].ACLR
reset => mem[14][6].ACLR
reset => mem[14][5].ACLR
reset => mem[14][4].ACLR
reset => mem[14][3].ACLR
reset => mem[14][2].ACLR
reset => mem[14][1].ACLR
reset => mem[14][0].ACLR
reset => mem[15][7].ACLR
reset => mem[15][6].ACLR
reset => mem[15][5].ACLR
reset => mem[15][4].ACLR
reset => mem[15][3].ACLR
reset => mem[15][2].ACLR
reset => mem[15][1].ACLR
reset => mem[15][0].ACLR
reset => mem[16][7].ACLR
reset => mem[16][6].ACLR
reset => mem[16][5].ACLR
reset => mem[16][4].ACLR
reset => mem[16][3].ACLR
reset => mem[16][2].ACLR
reset => mem[16][1].ACLR
reset => mem[16][0].ACLR
reset => mem[17][7].ACLR
reset => mem[17][6].ACLR
reset => mem[17][5].ACLR
reset => mem[17][4].ACLR
reset => mem[17][3].ACLR
reset => mem[17][2].ACLR
reset => mem[17][1].ACLR
reset => mem[17][0].ACLR
reset => mem[18][7].ACLR
reset => mem[18][6].ACLR
reset => mem[18][5].ACLR
reset => mem[18][4].ACLR
reset => mem[18][3].ACLR
reset => mem[18][2].ACLR
reset => mem[18][1].ACLR
reset => mem[18][0].ACLR
reset => mem[19][7].ACLR
reset => mem[19][6].ACLR
reset => mem[19][5].ACLR
reset => mem[19][4].ACLR
reset => mem[19][3].ACLR
reset => mem[19][2].ACLR
reset => mem[19][1].ACLR
reset => mem[19][0].ACLR
reset => mem[20][7].ACLR
reset => mem[20][6].ACLR
reset => mem[20][5].ACLR
reset => mem[20][4].ACLR
reset => mem[20][3].ACLR
reset => mem[20][2].ACLR
reset => mem[20][1].ACLR
reset => mem[20][0].ACLR
reset => mem[21][7].ACLR
reset => mem[21][6].ACLR
reset => mem[21][5].ACLR
reset => mem[21][4].ACLR
reset => mem[21][3].ACLR
reset => mem[21][2].ACLR
reset => mem[21][1].ACLR
reset => mem[21][0].ACLR
reset => mem[22][7].ACLR
reset => mem[22][6].ACLR
reset => mem[22][5].ACLR
reset => mem[22][4].ACLR
reset => mem[22][3].ACLR
reset => mem[22][2].ACLR
reset => mem[22][1].ACLR
reset => mem[22][0].ACLR
reset => mem[23][7].ACLR
reset => mem[23][6].ACLR
reset => mem[23][5].ACLR
reset => mem[23][4].ACLR
reset => mem[23][3].ACLR
reset => mem[23][2].ACLR
reset => mem[23][1].ACLR
reset => mem[23][0].ACLR
reset => mem[24][7].ACLR
reset => mem[24][6].ACLR
reset => mem[24][5].ACLR
reset => mem[24][4].ACLR
reset => mem[24][3].ACLR
reset => mem[24][2].ACLR
reset => mem[24][1].ACLR
reset => mem[24][0].ACLR
reset => mem[25][7].ACLR
reset => mem[25][6].ACLR
reset => mem[25][5].ACLR
reset => mem[25][4].ACLR
reset => mem[25][3].ACLR
reset => mem[25][2].ACLR
reset => mem[25][1].ACLR
reset => mem[25][0].ACLR
reset => mem[26][7].ACLR
reset => mem[26][6].ACLR
reset => mem[26][5].ACLR
reset => mem[26][4].ACLR
reset => mem[26][3].ACLR
reset => mem[26][2].ACLR
reset => mem[26][1].ACLR
reset => mem[26][0].ACLR
reset => mem[27][7].ACLR
reset => mem[27][6].ACLR
reset => mem[27][5].ACLR
reset => mem[27][4].ACLR
reset => mem[27][3].ACLR
reset => mem[27][2].ACLR
reset => mem[27][1].ACLR
reset => mem[27][0].ACLR
reset => mem[28][7].ACLR
reset => mem[28][6].ACLR
reset => mem[28][5].ACLR
reset => mem[28][4].ACLR
reset => mem[28][3].ACLR
reset => mem[28][2].ACLR
reset => mem[28][1].ACLR
reset => mem[28][0].ACLR
reset => mem[29][7].ACLR
reset => mem[29][6].ACLR
reset => mem[29][5].ACLR
reset => mem[29][4].ACLR
reset => mem[29][3].ACLR
reset => mem[29][2].ACLR
reset => mem[29][1].ACLR
reset => mem[29][0].ACLR
reset => mem[30][7].ACLR
reset => mem[30][6].ACLR
reset => mem[30][5].ACLR
reset => mem[30][4].ACLR
reset => mem[30][3].ACLR
reset => mem[30][2].ACLR
reset => mem[30][1].ACLR
reset => mem[30][0].ACLR
reset => mem[31][7].ACLR
reset => mem[31][6].ACLR
reset => mem[31][5].ACLR
reset => mem[31][4].ACLR
reset => mem[31][3].ACLR
reset => mem[31][2].ACLR
reset => mem[31][1].ACLR
reset => mem[31][0].ACLR
reset => sysbus[7].ACLR
reset => sysbus[6].ACLR
reset => sysbus[5].ACLR
reset => sysbus[4].ACLR
reset => sysbus[3].ACLR
reset => sysbus[2].ACLR
reset => sysbus[1].ACLR
reset => sysbus[0].ACLR
reset => count[4].ACLR
reset => op[2].ENA
reset => op[1].ENA
reset => op[0].ENA
reset => IR_out[7].ENA
reset => IR_out[6].ENA
reset => IR_out[5].ENA
reset => IR_out[4].ENA
reset => IR_out[3].ENA
reset => IR_out[2].ENA
reset => IR_out[1].ENA
reset => IR_out[0].ENA
reset => acc_out[7].ENA
reset => acc_out[6].ENA
reset => acc_out[5].ENA
reset => acc_out[4].ENA
reset => acc_out[3].ENA
reset => acc_out[2].ENA
reset => acc_out[1].ENA
reset => acc_out[0].ENA
reset => mdr_out[7].ENA
reset => mdr_out[6].ENA
reset => mdr_out[5].ENA
reset => mdr_out[4].ENA
reset => mdr_out[3].ENA
reset => mdr_out[2].ENA
reset => mdr_out[1].ENA
reset => mdr_out[0].ENA
reset => mar_out[4].ENA
reset => mar_out[3].ENA
reset => mar_out[2].ENA
reset => mar_out[1].ENA
reset => mar_out[0].ENA
reset => present_state~1.IN1
mode[0] => Mux~16.IN5
mode[0] => Mux~17.IN10
mode[0] => Mux~18.IN5
mode[0] => Mux~19.IN5
mode[0] => Mux~20.IN3
mode[0] => Mux~21.IN3
mode[0] => Mux~22.IN2
mode[0] => Mux~23.IN2
mode[0] => Mux~24.IN2
mode[1] => Mux~16.IN4
mode[1] => Mux~17.IN9
mode[1] => Mux~18.IN4
mode[1] => Mux~19.IN4
mode[1] => Mux~20.IN2
mode[1] => Mux~21.IN2
mode[1] => Mux~22.IN1
mode[1] => Mux~23.IN1
mode[1] => Mux~24.IN1
mode[2] => Mux~16.IN3
mode[2] => Mux~17.IN8
mode[2] => Mux~18.IN3
mode[2] => Mux~19.IN3
mode[2] => Mux~20.IN1
mode[2] => Mux~21.IN1
mode[2] => Mux~22.IN0
mode[2] => Mux~23.IN0
mode[2] => Mux~24.IN0
mem_addr[0] => Mux~8.IN4
mem_addr[0] => Mux~9.IN4
mem_addr[0] => Mux~10.IN4
mem_addr[0] => Mux~11.IN4
mem_addr[0] => Mux~12.IN4
mem_addr[0] => Mux~13.IN4
mem_addr[0] => Mux~14.IN4
mem_addr[0] => Mux~15.IN4
mem_addr[1] => Mux~8.IN3
mem_addr[1] => Mux~9.IN3
mem_addr[1] => Mux~10.IN3
mem_addr[1] => Mux~11.IN3
mem_addr[1] => Mux~12.IN3
mem_addr[1] => Mux~13.IN3
mem_addr[1] => Mux~14.IN3
mem_addr[1] => Mux~15.IN3
mem_addr[2] => Mux~8.IN2
mem_addr[2] => Mux~9.IN2
mem_addr[2] => Mux~10.IN2
mem_addr[2] => Mux~11.IN2
mem_addr[2] => Mux~12.IN2
mem_addr[2] => Mux~13.IN2
mem_addr[2] => Mux~14.IN2
mem_addr[2] => Mux~15.IN2
mem_addr[3] => Mux~8.IN1
mem_addr[3] => Mux~9.IN1
mem_addr[3] => Mux~10.IN1
mem_addr[3] => Mux~11.IN1
mem_addr[3] => Mux~12.IN1
mem_addr[3] => Mux~13.IN1
mem_addr[3] => Mux~14.IN1
mem_addr[3] => Mux~15.IN1
mem_addr[4] => Mux~8.IN0
mem_addr[4] => Mux~9.IN0
mem_addr[4] => Mux~10.IN0
mem_addr[4] => Mux~11.IN0
mem_addr[4] => Mux~12.IN0
mem_addr[4] => Mux~13.IN0
mem_addr[4] => Mux~14.IN0
mem_addr[4] => Mux~15.IN0
PC_bus <= present_state.s0
load_PC <= present_state.s9
INC_PC <= present_state.s0
Addr_bus <= present_state.s3
load_IR <= present_state.s2
ACC_bus <= present_state.s4
load_ACC <= present_state.s7
ALU_ACC <= present_state.s8
ALU_add <= ALU_add~0
ALU_sub <= ALU_sub~1
z_flag <= z_flag~reg0
MDR_bus <= reduce_or~6
load_MDR <= present_state.s4
load_MAR <= load_MAR~0
CS <= reduce_or~5
R_NW <= R_NW~0
sysbus_out[0] <= sysbus[0].DB_MAX_OUTPUT_PORT_TYPE
sysbus_out[1] <= sysbus[1].DB_MAX_OUTPUT_PORT_TYPE
sysbus_out[2] <= sysbus[2].DB_MAX_OUTPUT_PORT_TYPE
sysbus_out[3] <= sysbus[3].DB_MAX_OUTPUT_PORT_TYPE
sysbus_out[4] <= sysbus[4].DB_MAX_OUTPUT_PORT_TYPE
sysbus_out[5] <= sysbus[5].DB_MAX_OUTPUT_PORT_TYPE
sysbus_out[6] <= sysbus[6].DB_MAX_OUTPUT_PORT_TYPE
sysbus_out[7] <= sysbus[7].DB_MAX_OUTPUT_PORT_TYPE
present_out[0] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
present_out[1] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
present_out[2] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
present_out[3] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
output[0] <= process2~8.DB_MAX_OUTPUT_PORT_TYPE
output[1] <= process2~7.DB_MAX_OUTPUT_PORT_TYPE
output[2] <= process2~6.DB_MAX_OUTPUT_PORT_TYPE
output[3] <= process2~5.DB_MAX_OUTPUT_PORT_TYPE
output[4] <= process2~4.DB_MAX_OUTPUT_PORT_TYPE
output[5] <= process2~3.DB_MAX_OUTPUT_PORT_TYPE
output[6] <= process2~2.DB_MAX_OUTPUT_PORT_TYPE
output[7] <= process2~1.DB_MAX_OUTPUT_PORT_TYPE