cpu.map.qmsg

说明：cpuyuanma1是硬布线控制器源代码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "IR_out\[7\] op\[2\] " "Info: Duplicate register \"IR_out\[7\]\" merged to single register \"op\[2\]\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 53 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "IR_out\[6\] op\[1\] " "Info: Duplicate register \"IR_out\[6\]\" merged to single register \"op\[1\]\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 53 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "IR_out\[5\] op\[0\] " "Info: Duplicate register \"IR_out\[5\]\" merged to single register \"op\[0\]\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 53 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|CPU\|present_state 11 0 " "Info: State machine \"\|CPU\|present_state\" contains 11 states and 0 state bits" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 50 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|CPU\|present_state " "Info: Selected Auto state machine encoding method for state machine \"\|CPU\|present_state\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 50 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|CPU\|present_state " "Info: Encoding result for state machine \"\|CPU\|present_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "11 " "Info: Completed encoding using 11 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s10 " "Info: Encoded state bit \"present_state.s10\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s9 " "Info: Encoded state bit \"present_state.s9\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s8 " "Info: Encoded state bit \"present_state.s8\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s7 " "Info: Encoded state bit \"present_state.s7\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s6 " "Info: Encoded state bit \"present_state.s6\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s5 " "Info: Encoded state bit \"present_state.s5\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s4 " "Info: Encoded state bit \"present_state.s4\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s3 " "Info: Encoded state bit \"present_state.s3\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s2 " "Info: Encoded state bit \"present_state.s2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s1 " "Info: Encoded state bit \"present_state.s1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "present_state.s0 " "Info: Encoded state bit \"present_state.s0\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s0 00000000000 " "Info: State \"\|CPU\|present_state.s0\" uses code string \"00000000000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s1 00000000011 " "Info: State \"\|CPU\|present_state.s1\" uses code string \"00000000011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s2 00000000101 " "Info: State \"\|CPU\|present_state.s2\" uses code string \"00000000101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s3 00000001001 " "Info: State \"\|CPU\|present_state.s3\" uses code string \"00000001001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s4 00000010001 " "Info: State \"\|CPU\|present_state.s4\" uses code string \"00000010001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s5 00000100001 " "Info: State \"\|CPU\|present_state.s5\" uses code string \"00000100001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s6 00001000001 " "Info: State \"\|CPU\|present_state.s6\" uses code string \"00001000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s7 00010000001 " "Info: State \"\|CPU\|present_state.s7\" uses code string \"00010000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s8 00100000001 " "Info: State \"\|CPU\|present_state.s8\" uses code string \"00100000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s9 01000000001 " "Info: State \"\|CPU\|present_state.s9\" uses code string \"01000000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|CPU\|present_state.s10 10000000001 " "Info: State \"\|CPU\|present_state.s10\" uses code string \"10000000001\"" {  } {  } 0}  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 50 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_HDR" "" "Info: One or more bidirs are fed by always enabled tri-state buffers" { { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "PC_bus " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"PC_bus\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 12 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "load_PC " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"load_PC\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 13 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "INC_PC " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"INC_PC\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "Addr_bus " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"Addr_bus\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "load_IR " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"load_IR\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "ACC_bus " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"ACC_bus\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 19 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "load_ACC " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"load_ACC\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 20 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "ALU_ACC " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"ALU_ACC\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 21 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "ALU_add " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"ALU_add\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 22 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "ALU_sub " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"ALU_sub\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 23 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "z_flag " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"z_flag\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 24 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "MDR_bus " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"MDR_bus\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 26 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "load_MDR " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"load_MDR\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 27 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "load_MAR " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"load_MAR\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 28 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "CS " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"CS\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 29 -1 0 } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "R_NW " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"R_NW\" is moved to its source" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 30 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "PC_bus~1 " "Warning: Node \"PC_bus~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "load_PC~1 " "Warning: Node \"load_PC~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "INC_PC~1 " "Warning: Node \"INC_PC~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 14 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "Addr_bus~1 " "Warning: Node \"Addr_bus~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 16 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "load_IR~1 " "Warning: Node \"load_IR~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 17 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "ACC_bus~1 " "Warning: Node \"ACC_bus~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 19 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "load_ACC~1 " "Warning: Node \"load_ACC~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 20 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "ALU_ACC~1 " "Warning: Node \"ALU_ACC~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 21 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "ALU_add~3 " "Warning: Node \"ALU_add~3\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 22 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "ALU_sub~5 " "Warning: Node \"ALU_sub~5\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 23 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "z_flag~1 " "Warning: Node \"z_flag~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 24 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "MDR_bus~1 " "Warning: Node \"MDR_bus~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "load_MDR~1 " "Warning: Node \"load_MDR~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 27 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "load_MAR~2 " "Warning: Node \"load_MAR~2\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 28 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "CS~1 " "Warning: Node \"CS~1\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 29 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "R_NW~2 " "Warning: Node \"R_NW~2\"" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "902 " "Info: Implemented 902 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "856 " "Info: Implemented 856 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 23 16:32:57 2005 " "Info: Processing ended: Tue Aug 23 16:32:57 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0}  } {  } 0}