cpu.map.qmsg

说明：cpuyuanma1是硬布线控制器源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 23 16:32:45 2005 " "Info: Processing started: Tue Aug 23 16:32:45 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_defs.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file cpu_defs.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpu_defs " "Info: Found design unit 1: cpu_defs" {  } { { "cpu_defs.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu_defs.vhd" 5 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 cpu_defs-body " "Info: Found design unit 2: cpu_defs-body" {  } { { "cpu_defs.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu_defs.vhd" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cpu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CPU-rtl " "Info: Found design unit 1: CPU-rtl" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 38 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 CPU " "Info: Found entity 1: CPU" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CPU " "Info: Elaborating entity \"CPU\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count cpu.vhd(269) " "Warning: VHDL Process Statement warning at cpu.vhd(269): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 269 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "op cpu.vhd(271) " "Warning: VHDL Process Statement warning at cpu.vhd(271): signal \"op\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 271 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mdr_out cpu.vhd(273) " "Warning: VHDL Process Statement warning at cpu.vhd(273): signal \"mdr_out\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 273 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mar_out cpu.vhd(275) " "Warning: VHDL Process Statement warning at cpu.vhd(275): signal \"mar_out\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 275 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "IR_out cpu.vhd(277) " "Warning: VHDL Process Statement warning at cpu.vhd(277): signal \"IR_out\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 277 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "acc_out cpu.vhd(279) " "Warning: VHDL Process Statement warning at cpu.vhd(279): signal \"acc_out\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 279 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mem cpu.vhd(281) " "Warning: VHDL Process Statement warning at cpu.vhd(281): signal \"mem\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 281 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "count\[0\]~10 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: \"count\[0\]~10\"" {  } { { "cpu.vhd" "count\[0\]~10" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 56 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}