📄 cpu.tan.qmsg

📁 说明：cpuyuanma1是硬布线控制器源代码
💻 QMSG
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{ "Info" "ITDB_FULL_TPD_RESULT" "mem_addr\[0\] output\[2\] 42.400 ns Longest " "Info: Longest tpd from source pin \"mem_addr\[0\]\" to destination pin \"output\[2\]\" is 42.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns mem_addr\[0\] 1 PIN PIN_67 60 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_67; Fanout = 60; PIN Node = 'mem_addr\[0\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { mem_addr[0] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.800 ns) + CELL(2.000 ns) 10.900 ns Mux~2091 2 COMB LC8_F25 1 " "Info: 2: + IC(5.800 ns) + CELL(2.000 ns) = 10.900 ns; Loc. = LC8_F25; Fanout = 1; COMB Node = 'Mux~2091'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "7.800 ns" { mem_addr[0] Mux~2091 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 13.100 ns Mux~2092 3 COMB LC3_F25 1 " "Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 13.100 ns; Loc. = LC3_F25; Fanout = 1; COMB Node = 'Mux~2092'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "2.200 ns" { Mux~2091 Mux~2092 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(2.200 ns) 19.200 ns Mux~2093 4 COMB LC6_I22 1 " "Info: 4: + IC(3.900 ns) + CELL(2.200 ns) = 19.200 ns; Loc. = LC6_I22; Fanout = 1; COMB Node = 'Mux~2093'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "6.100 ns" { Mux~2092 Mux~2093 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(2.000 ns) 25.300 ns Mux~2096 5 COMB LC6_F3 1 " "Info: 5: + IC(4.100 ns) + CELL(2.000 ns) = 25.300 ns; Loc. = LC6_F3; Fanout = 1; COMB Node = 'Mux~2096'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "6.100 ns" { Mux~2093 Mux~2096 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 27.500 ns Mux~2107 6 COMB LC7_F3 1 " "Info: 6: + IC(0.200 ns) + CELL(2.000 ns) = 27.500 ns; Loc. = LC7_F3; Fanout = 1; COMB Node = 'Mux~2107'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "2.200 ns" { Mux~2096 Mux~2107 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.700 ns) 31.000 ns Mux~2111 7 COMB LC5_F2 1 " "Info: 7: + IC(1.800 ns) + CELL(1.700 ns) = 31.000 ns; Loc. = LC5_F2; Fanout = 1; COMB Node = 'Mux~2111'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "3.500 ns" { Mux~2107 Mux~2111 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(8.600 ns) 42.400 ns output\[2\] 8 PIN PIN_113 0 " "Info: 8: + IC(2.800 ns) + CELL(8.600 ns) = 42.400 ns; Loc. = PIN_113; Fanout = 0; PIN Node = 'output\[2\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "11.400 ns" { Mux~2111 output[2] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.600 ns 55.66 % " "Info: Total cell delay = 23.600 ns ( 55.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.800 ns 44.34 % " "Info: Total interconnect delay = 18.800 ns ( 44.34 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "42.400 ns" { mem_addr[0] Mux~2091 Mux~2092 Mux~2093 Mux~2096 Mux~2107 Mux~2111 output[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "42.400 ns" { mem_addr[0] mem_addr[0]~out Mux~2091 Mux~2092 Mux~2093 Mux~2096 Mux~2107 Mux~2111 output[2] } { 0.000ns 0.000ns 5.800ns 0.200ns 3.900ns 4.100ns 0.200ns 1.800ns 2.800ns } { 0.000ns 3.100ns 2.000ns 2.000ns 2.200ns 2.000ns 2.000ns 1.700ns 8.600ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "mar_out\[4\] reset clock -5.300 ns register " "Info: th for register \"mar_out\[4\]\" (data pin = \"reset\", clock pin = \"clock\") is -5.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 345 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 345; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { clock } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns mar_out\[4\] 2 REG LC4_F15 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_F15; Fanout = 1; REG Node = 'mar_out\[4\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.400 ns" { clock mar_out[4] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mar_out[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mar_out[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns reset 1 PIN PIN_83 345 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_83; Fanout = 345; PIN Node = 'reset'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { reset } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.300 ns) 8.100 ns mar_out\[4\] 2 REG LC4_F15 1 " "Info: 2: + IC(4.700 ns) + CELL(0.300 ns) = 8.100 ns; Loc. = LC4_F15; Fanout = 1; REG Node = 'mar_out\[4\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "5.000 ns" { reset mar_out[4] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 41.98 % " "Info: Total cell delay = 3.400 ns ( 41.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 58.02 % " "Info: Total interconnect delay = 4.700 ns ( 58.02 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "8.100 ns" { reset mar_out[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.100 ns" { reset reset~out mar_out[4] } { 0.000ns 0.000ns 4.700ns } { 0.000ns 3.100ns 0.300ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mar_out[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mar_out[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "8.100 ns" { reset mar_out[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.100 ns" { reset reset~out mar_out[4] } { 0.000ns 0.000ns 4.700ns } { 0.000ns 3.100ns 0.300ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock INC_PC present_state.s0~15 12.400 ns register " "Info: Minimum tco from clock \"clock\" to destination pin \"INC_PC\" through register \"present_state.s0~15\" is 12.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 345 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 345; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { clock } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns present_state.s0~15 2 REG LC7_F37 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_F37; Fanout = 1; REG Node = 'present_state.s0~15'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.400 ns" { clock present_state.s0~15 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock present_state.s0~15 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out present_state.s0~15 } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.5ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.400 ns + Shortest register pin " "Info: + Shortest register to pin delay is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns present_state.s0~15 1 REG LC7_F37 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_F37; Fanout = 1; REG Node = 'present_state.s0~15'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/
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