cpu.tan.qmsg

说明：cpuyuanma1是硬布线控制器源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register mar\[1\] register mdr_out\[7\] 40.98 MHz 24.4 ns Internal " "Info: Clock \"clock\" has Internal fmax of 40.98 MHz between source register \"mar\[1\]\" and destination register \"mdr_out\[7\]\" (period= 24.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.600 ns + Longest register register " "Info: + Longest register to register delay is 22.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mar\[1\] 1 REG LC1_F22 78 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F22; Fanout = 78; REG Node = 'mar\[1\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { mar[1] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(2.000 ns) 6.500 ns Mux~2017 2 COMB LC1_I34 1 " "Info: 2: + IC(4.500 ns) + CELL(2.000 ns) = 6.500 ns; Loc. = LC1_I34; Fanout = 1; COMB Node = 'Mux~2017'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "6.500 ns" { mar[1] Mux~2017 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 9.600 ns Mux~2018 3 COMB LC6_I33 1 " "Info: 3: + IC(1.100 ns) + CELL(2.000 ns) = 9.600 ns; Loc. = LC6_I33; Fanout = 1; COMB Node = 'Mux~2018'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "3.100 ns" { Mux~2017 Mux~2018 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 12.000 ns Mux~2019 4 COMB LC1_I33 1 " "Info: 4: + IC(0.200 ns) + CELL(2.200 ns) = 12.000 ns; Loc. = LC1_I33; Fanout = 1; COMB Node = 'Mux~2019'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "2.400 ns" { Mux~2018 Mux~2019 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.000 ns) 15.200 ns Mux~2022 5 COMB LC2_I40 1 " "Info: 5: + IC(1.200 ns) + CELL(2.000 ns) = 15.200 ns; Loc. = LC2_I40; Fanout = 1; COMB Node = 'Mux~2022'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "3.200 ns" { Mux~2019 Mux~2022 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 17.600 ns mdr~2422 6 COMB LC3_I40 1 " "Info: 6: + IC(0.200 ns) + CELL(2.200 ns) = 17.600 ns; Loc. = LC3_I40; Fanout = 1; COMB Node = 'mdr~2422'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "2.400 ns" { Mux~2022 mdr~2422 } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 19.500 ns mdr~2423 7 COMB LC5_I40 2 " "Info: 7: + IC(0.200 ns) + CELL(1.700 ns) = 19.500 ns; Loc. = LC5_I40; Fanout = 2; COMB Node = 'mdr~2423'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { mdr~2422 mdr~2423 } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 21.400 ns mdr~2424 8 COMB LC7_I40 2 " "Info: 8: + IC(0.200 ns) + CELL(1.700 ns) = 21.400 ns; Loc. = LC7_I40; Fanout = 2; COMB Node = 'mdr~2424'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { mdr~2423 mdr~2424 } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 64 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 22.600 ns mdr_out\[7\] 9 REG LC6_I40 1 " "Info: 9: + IC(0.200 ns) + CELL(1.000 ns) = 22.600 ns; Loc. = LC6_I40; Fanout = 1; REG Node = 'mdr_out\[7\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.200 ns" { mdr~2424 mdr_out[7] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.800 ns 65.49 % " "Info: Total cell delay = 14.800 ns ( 65.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.800 ns 34.51 % " "Info: Total interconnect delay = 7.800 ns ( 34.51 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "22.600 ns" { mar[1] Mux~2017 Mux~2018 Mux~2019 Mux~2022 mdr~2422 mdr~2423 mdr~2424 mdr_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.600 ns" { mar[1] Mux~2017 Mux~2018 Mux~2019 Mux~2022 mdr~2422 mdr~2423 mdr~2424 mdr_out[7] } { 0.000ns 4.500ns 1.100ns 0.200ns 1.200ns 0.200ns 0.200ns 0.200ns 0.200ns } { 0.000ns 2.000ns 2.000ns 2.200ns 2.000ns 2.200ns 1.700ns 1.700ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 345 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 345; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { clock } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns mdr_out\[7\] 2 REG LC6_I40 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_I40; Fanout = 1; REG Node = 'mdr_out\[7\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.400 ns" { clock mdr_out[7] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mdr_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mdr_out[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 345 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 345; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { clock } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns mar\[1\] 2 REG LC1_F22 78 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_F22; Fanout = 78; REG Node = 'mar\[1\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.400 ns" { clock mar[1] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 65 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mar[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mar[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mdr_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mdr_out[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mar[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mar[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 65 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 51 -1 0 } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "22.600 ns" { mar[1] Mux~2017 Mux~2018 Mux~2019 Mux~2022 mdr~2422 mdr~2423 mdr~2424 mdr_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.600 ns" { mar[1] Mux~2017 Mux~2018 Mux~2019 Mux~2022 mdr~2422 mdr~2423 mdr~2424 mdr_out[7] } { 0.000ns 4.500ns 1.100ns 0.200ns 1.200ns 0.200ns 0.200ns 0.200ns 0.200ns } { 0.000ns 2.000ns 2.000ns 2.200ns 2.000ns 2.200ns 1.700ns 1.700ns 1.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mdr_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mdr_out[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mar[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mar[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "mdr_out\[3\] reset clock 9.400 ns register " "Info: tsu for register \"mdr_out\[3\]\" (data pin = \"reset\", clock pin = \"clock\") is 9.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.600 ns + Longest pin register " "Info: + Longest pin to register delay is 10.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns reset 1 PIN PIN_83 345 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_83; Fanout = 345; PIN Node = 'reset'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { reset } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.200 ns) + CELL(0.300 ns) 10.600 ns mdr_out\[3\] 2 REG LC2_F51 1 " "Info: 2: + IC(7.200 ns) + CELL(0.300 ns) = 10.600 ns; Loc. = LC2_F51; Fanout = 1; REG Node = 'mdr_out\[3\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "7.500 ns" { reset mdr_out[3] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 32.08 % " "Info: Total cell delay = 3.400 ns ( 32.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns 67.92 % " "Info: Total interconnect delay = 7.200 ns ( 67.92 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "10.600 ns" { reset mdr_out[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.600 ns" { reset reset~out mdr_out[3] } { 0.000ns 0.000ns 7.200ns } { 0.000ns 3.100ns 0.300ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 51 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 345 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 345; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { clock } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns mdr_out\[3\] 2 REG LC2_F51 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_F51; Fanout = 1; REG Node = 'mdr_out\[3\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.400 ns" { clock mdr_out[3] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mdr_out[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mdr_out[3] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "10.600 ns" { reset mdr_out[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.600 ns" { reset reset~out mdr_out[3] } { 0.000ns 0.000ns 7.200ns } { 0.000ns 3.100ns 0.300ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mdr_out[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mdr_out[3] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock output\[3\] mem\[18\]\[3\] 40.500 ns register " "Info: tco from clock \"clock\" to destination pin \"output\[3\]\" through register \"mem\[18\]\[3\]\" is 40.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 345 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 345; CLK Node = 'clock'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { clock } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns mem\[18\]\[3\] 2 REG LC2_I38 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_I38; Fanout = 2; REG Node = 'mem\[18\]\[3\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.400 ns" { clock mem[18][3] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mem[18][3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mem[18][3] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "37.500 ns + Longest register pin " "Info: + Longest register to pin delay is 37.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mem\[18\]\[3\] 1 REG LC2_I38 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_I38; Fanout = 2; REG Node = 'mem\[18\]\[3\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "" { mem[18][3] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.200 ns) 5.100 ns Mux~2117 2 COMB LC7_J43 1 " "Info: 2: + IC(2.900 ns) + CELL(2.200 ns) = 5.100 ns; Loc. = LC7_J43; Fanout = 1; COMB Node = 'Mux~2117'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "5.100 ns" { mem[18][3] Mux~2117 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 7.300 ns Mux~2118 3 COMB LC8_J43 1 " "Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 7.300 ns; Loc. = LC8_J43; Fanout = 1; COMB Node = 'Mux~2118'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "2.200 ns" { Mux~2117 Mux~2118 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.900 ns) 10.900 ns Mux~2121 4 COMB LC8_J42 1 " "Info: 4: + IC(1.700 ns) + CELL(1.900 ns) = 10.900 ns; Loc. = LC8_J42; Fanout = 1; COMB Node = 'Mux~2121'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "3.600 ns" { Mux~2118 Mux~2121 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 13.100 ns Mux~2124 5 COMB LC6_J42 1 " "Info: 5: + IC(0.200 ns) + CELL(2.000 ns) = 13.100 ns; Loc. = LC6_J42; Fanout = 1; COMB Node = 'Mux~2124'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "2.200 ns" { Mux~2121 Mux~2124 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(1.700 ns) 19.300 ns Mux~2135 6 COMB LC8_F13 1 " "Info: 6: + IC(4.500 ns) + CELL(1.700 ns) = 19.300 ns; Loc. = LC8_F13; Fanout = 1; COMB Node = 'Mux~2135'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "6.200 ns" { Mux~2124 Mux~2135 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.200 ns) 23.600 ns Mux~2136 7 COMB LC8_F32 1 " "Info: 7: + IC(2.100 ns) + CELL(2.200 ns) = 23.600 ns; Loc. = LC8_F32; Fanout = 1; COMB Node = 'Mux~2136'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "4.300 ns" { Mux~2135 Mux~2136 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 25.700 ns Mux~2137 8 COMB LC1_F32 1 " "Info: 8: + IC(0.200 ns) + CELL(1.900 ns) = 25.700 ns; Loc. = LC1_F32; Fanout = 1; COMB Node = 'Mux~2137'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "2.100 ns" { Mux~2136 Mux~2137 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(8.600 ns) 37.500 ns output\[3\] 9 PIN PIN_114 0 " "Info: 9: + IC(3.200 ns) + CELL(8.600 ns) = 37.500 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'output\[3\]'" {  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "11.800 ns" { Mux~2137 output[3] } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "22.500 ns 60.00 % " "Info: Total cell delay = 22.500 ns ( 60.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.000 ns 40.00 % " "Info: Total interconnect delay = 15.000 ns ( 40.00 % )" {  } {  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "37.500 ns" { mem[18][3] Mux~2117 Mux~2118 Mux~2121 Mux~2124 Mux~2135 Mux~2136 Mux~2137 output[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "37.500 ns" { mem[18][3] Mux~2117 Mux~2118 Mux~2121 Mux~2124 Mux~2135 Mux~2136 Mux~2137 output[3] } { 0.000ns 2.900ns 0.200ns 1.700ns 0.200ns 4.500ns 2.100ns 0.200ns 3.200ns } { 0.000ns 2.200ns 2.000ns 1.900ns 2.000ns 1.700ns 2.200ns 1.900ns 8.600ns } } }  } 0}  } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "1.900 ns" { clock mem[18][3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out mem[18][3] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/db/cpu.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/" "" "37.500 ns" { mem[18][3] Mux~2117 Mux~2118 Mux~2121 Mux~2124 Mux~2135 Mux~2136 Mux~2137 output[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "37.500 ns" { mem[18][3] Mux~2117 Mux~2118 Mux~2121 Mux~2124 Mux~2135 Mux~2136 Mux~2137 output[3] } { 0.000ns 2.900ns 0.200ns 1.700ns 0.200ns 4.500ns 2.100ns 0.200ns 3.200ns } { 0.000ns 2.200ns 2.000ns 1.900ns 2.000ns 1.700ns 2.200ns 1.900ns 8.600ns } } }  } 0}