cpu.map.rpt

说明：cpuyuanma1是硬布线控制器源代码

+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_2 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 9           ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_5ih ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/11-logical controller/cpu.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Aug 23 16:32:45 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu
Info: Found 2 design units, including 0 entities, in source file cpu_defs.vhd
    Info: Found design unit 1: cpu_defs
    Info: Found design unit 2: cpu_defs-body
Info: Found 2 design units, including 1 entities, in source file cpu.vhd
    Info: Found design unit 1: CPU-rtl
    Info: Found entity 1: CPU
Info: Elaborating entity "CPU" for the top level hierarchy
Warning: VHDL Process Statement warning at cpu.vhd(269): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(271): signal "op" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(273): signal "mdr_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(275): signal "mar_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(277): signal "IR_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(279): signal "acc_out" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at cpu.vhd(281): signal "mem" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "count[0]~10"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
    Info: Duplicate register "IR_out[7]" merged to single register "op[2]"
    Info: Duplicate register "IR_out[6]" merged to single register "op[1]"
    Info: Duplicate register "IR_out[5]" merged to single register "op[0]"
Info: State machine "|CPU|present_state" contains 11 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|CPU|present_state"
Info: Encoding result for state machine "|CPU|present_state"
    Info: Completed encoding using 11 state bits
        Info: Encoded state bit "present_state.s10"
        Info: Encoded state bit "present_state.s9"
        Info: Encoded state bit "present_state.s8"
        Info: Encoded state bit "present_state.s7"
        Info: Encoded state bit "present_state.s6"
        Info: Encoded state bit "present_state.s5"
        Info: Encoded state bit "present_state.s4"
        Info: Encoded state bit "present_state.s3"
        Info: Encoded state bit "present_state.s2"
        Info: Encoded state bit "present_state.s1"
        Info: Encoded state bit "present_state.s0"
    Info: State "|CPU|present_state.s0" uses code string "00000000000"
    Info: State "|CPU|present_state.s1" uses code string "00000000011"
    Info: State "|CPU|present_state.s2" uses code string "00000000101"
    Info: State "|CPU|present_state.s3" uses code string "00000001001"
    Info: State "|CPU|present_state.s4" uses code string "00000010001"
    Info: State "|CPU|present_state.s5" uses code string "00000100001"
    Info: State "|CPU|present_state.s6" uses code string "00001000001"
    Info: State "|CPU|present_state.s7" uses code string "00010000001"
    Info: State "|CPU|present_state.s8" uses code string "00100000001"
    Info: State "|CPU|present_state.s9" uses code string "01000000001"
    Info: State "|CPU|present_state.s10" uses code string "10000000001"
Info: One or more bidirs are fed by always enabled tri-state buffers
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "PC_bus" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "load_PC" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "INC_PC" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "Addr_bus" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "load_IR" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ACC_bus" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "load_ACC" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ALU_ACC" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ALU_add" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "ALU_sub" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "z_flag" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "MDR_bus" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "load_MDR" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "load_MAR" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "CS" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "R_NW" is moved to its source
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "PC_bus~1"
    Warning: Node "load_PC~1"
    Warning: Node "INC_PC~1"
    Warning: Node "Addr_bus~1"
    Warning: Node "load_IR~1"
    Warning: Node "ACC_bus~1"
    Warning: Node "load_ACC~1"
    Warning: Node "ALU_ACC~1"
    Warning: Node "ALU_add~3"
    Warning: Node "ALU_sub~5"
    Warning: Node "z_flag~1"
    Warning: Node "MDR_bus~1"
    Warning: Node "load_MDR~1"
    Warning: Node "load_MAR~2"
    Warning: Node "CS~1"
    Warning: Node "R_NW~2"
Info: Registers with preset signals will power-up high
Info: Implemented 902 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 20 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 856 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Processing ended: Tue Aug 23 16:32:57 2005
    Info: Elapsed time: 00:00:12