readme_asm_hostboot.txt

TS201 HOSTBOOT源代码 学习TS201 HOSTHOOT

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       ADSP-TS201S EZ-Kit Host Boot routine

Sets up slave (DSPA) in host boot mode and the master (DSPB) boots the slave via
Autodma0 with an example alternating led blink code using bootdata.ldr. The project
Bootdata to create bootdata.ldr is also attached. 

Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062

MARCH-2004 BL

This directory contains an example ADSP-TS101S subroutines that 
implement host boot. 


Files contained in this directory:

ADSP-TS201_ASM_MP.ldf			Linker description file for Host Boot project
HostBoot.dpj				VisualDSP project file for Host Boot project
MasterDSPB.asm				Source file for DSPB for Host Boot project
SlaveDSPA.asm				Source file for DSPA for Host Boot project
ADSP-TS201_ASM.ldf			Linker description file for Bootdata project
bootdata.dpj				VisualDSP project file for Bootdata project
bootcode.asm				Source file for Bootdata project
TSEZKitDef.h				TS201S EZ-Kit define file
README_ASM_HOSTBOOT.txt			This README file
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CONTENTS

I.    SLAVE CODE (SlaveDSPA) DESCRIPTION
II.   MASTER CODE (MasterDSPB) DESCRIPTION
III.  BOOTED CODE (bootdata) DESCRIPTION
IV.   RUNNING PROJECT DESCRIPTION
         

I. SLAVE CODE (SlaveDSPA) DESCRIPTION

The Slave code is in SlaveDSPA.asm.

Normally, when the TigerSHARC is to be booted from a host, it is at IDLE with
both AutoDMAs and vector interrupts enabled. Since in this example the slave
would already have been interrupted out of IDLE (via either a PROM boot or an
emulation interrupt), SlaveDSPA is designed to send the chip into a state
identical to power-on state before a host boot. It enables the AutoDMA0 and 
vector interrupts. After these initializations, the processor sits at IDLE
waiting for the master to boot it.

II.   MASTER CODE (MasterDSPB) DESCRIPTION

MasterDSPB.asm contains the master code that boots the slave (DSPA). First, the
code delays for some time to insure that the slave is ready (since in this case,
unlike a generic host boot, the slave actually needs to run the SlaveDSPA code).
The host then sends the data from bootdata.ldr to AutoDMA0 of the slave. The slave
throttles data being sent to it by locking the bus until its DMA is ready to receive.
After the DSPA's AUTODMA0 receives the data, there will be a delay of up to 12 CCLK 
cycles before the AUTODMA0's ISR is serviced and bus lock is enabled. Any data sent to
AUTODMA0 during this time will be lost. Thus, the host must insert waits of at least
12*LCLKRAT external cycles between each write to the AUTODMA0 register of the slave DSP
to ensure proper boot. Additionally, master (DSPB) has an external port output FIFO, so
delayed writes to the external port may not guarantee the same delay between
the times when these transactions take place on the external port. If this output FIFO
has several transactions queued into it, when the slave DSP releases bus lock, all
of the queued transactions will come out back to back, resulting in loss of data, as above.
To take care of this issue, master (DSPB) inserts reads of a dummy address on the external
bus between	all writes to AUTODMA0 with a dependency on the read value. This makes
master code stall until	the read is finished, thus the following write will not be queued
into the FIFO until the read is finished, i.e. until the bus is unlocked.

III.  BOOTED CODE (bootdata) DESCRIPTION

This code is build in the project bootdata.dpj, its source is in bootdata.asm. 
This project selects (in the Project Options) Loader file as the Project type and 
Host as the boot type. The kernel file points to 
C:\Program Files\Analog Devices\VisualDSP\Ts\ldr\TS201_host.dxe. Since the slave
(DSPA) has ID0, the bootdata.ldr must target processor ID0.

IV.   RUNNING PROJECT DESCRIPTION

Load the project into the EZ-Kit through emulation, MasterDSPB into DSPB and
SlaveDSPA into DSPA. Execute Debug -> Multiprocessor -> Run. The slave (DSPA)
will be booted by the master (DSPB) and will start to alternatively toggle two
leds.