📄 niosii_system.v
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begin
if (cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module + cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_data_master_arbitrator (
// inputs:
clk,
cpu_0_data_master_address,
cpu_0_data_master_debugaccess,
cpu_0_data_master_granted_cpu_0_jtag_debug_module,
cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_granted_onchip_memory_0_s1,
cpu_0_data_master_granted_seg7_lut_8_0_avalon_slave_0,
cpu_0_data_master_granted_timer_0_s1,
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_qualified_request_onchip_memory_0_s1,
cpu_0_data_master_qualified_request_seg7_lut_8_0_avalon_slave_0,
cpu_0_data_master_qualified_request_timer_0_s1,
cpu_0_data_master_read,
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_read_data_valid_onchip_memory_0_s1,
cpu_0_data_master_read_data_valid_seg7_lut_8_0_avalon_slave_0,
cpu_0_data_master_read_data_valid_timer_0_s1,
cpu_0_data_master_requests_cpu_0_jtag_debug_module,
cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_requests_onchip_memory_0_s1,
cpu_0_data_master_requests_seg7_lut_8_0_avalon_slave_0,
cpu_0_data_master_requests_timer_0_s1,
cpu_0_data_master_write,
cpu_0_jtag_debug_module_readdata_from_sa,
d1_cpu_0_jtag_debug_module_end_xfer,
d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
d1_onchip_memory_0_s1_end_xfer,
d1_seg7_lut_8_0_avalon_slave_0_end_xfer,
d1_timer_0_s1_end_xfer,
jtag_uart_0_avalon_jtag_slave_irq_from_sa,
jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
onchip_memory_0_s1_readdata_from_sa,
registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1,
reset_n,
timer_0_s1_irq_from_sa,
timer_0_s1_readdata_from_sa,
// outputs:
cpu_0_data_master_address_to_slave,
cpu_0_data_master_irq,
cpu_0_data_master_readdata,
cpu_0_data_master_waitrequest
)
/* synthesis auto_dissolve = "FALSE" */ ;
output [ 16: 0] cpu_0_data_master_address_to_slave;
output [ 31: 0] cpu_0_data_master_irq;
output [ 31: 0] cpu_0_data_master_readdata;
output cpu_0_data_master_waitrequest;
input clk;
input [ 16: 0] cpu_0_data_master_address;
input cpu_0_data_master_debugaccess;
input cpu_0_data_master_granted_cpu_0_jtag_debug_module;
input cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_granted_onchip_memory_0_s1;
input cpu_0_data_master_granted_seg7_lut_8_0_avalon_slave_0;
input cpu_0_data_master_granted_timer_0_s1;
input cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
input cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_qualified_request_onchip_memory_0_s1;
input cpu_0_data_master_qualified_request_seg7_lut_8_0_avalon_slave_0;
input cpu_0_data_master_qualified_request_timer_0_s1;
input cpu_0_data_master_read;
input cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
input cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_read_data_valid_onchip_memory_0_s1;
input cpu_0_data_master_read_data_valid_seg7_lut_8_0_avalon_slave_0;
input cpu_0_data_master_read_data_valid_timer_0_s1;
input cpu_0_data_master_requests_cpu_0_jtag_debug_module;
input cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_requests_onchip_memory_0_s1;
input cpu_0_data_master_requests_seg7_lut_8_0_avalon_slave_0;
input cpu_0_data_master_requests_timer_0_s1;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
input d1_cpu_0_jtag_debug_module_end_xfer;
input d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
input d1_onchip_memory_0_s1_end_xfer;
input d1_seg7_lut_8_0_avalon_slave_0_end_xfer;
input d1_timer_0_s1_end_xfer;
input jtag_uart_0_avalon_jtag_slave_irq_from_sa;
input [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
input jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
input [ 31: 0] onchip_memory_0_s1_readdata_from_sa;
input registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1;
input reset_n;
input timer_0_s1_irq_from_sa;
input [ 15: 0] timer_0_s1_readdata_from_sa;
wire [ 16: 0] cpu_0_data_master_address_to_slave;
wire [ 31: 0] cpu_0_data_master_irq;
wire [ 31: 0] cpu_0_data_master_readdata;
wire cpu_0_data_master_run;
reg cpu_0_data_master_waitrequest;
wire [ 31: 0] p1_registered_cpu_0_data_master_readdata;
wire r_0;
wire r_1;
reg [ 31: 0] registered_cpu_0_data_master_readdata;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) & (cpu_0_data_master_granted_cpu_0_jtag_debug_module | ~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_onchip_memory_0_s1 | registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 | ~cpu_0_data_master_requests_onchip_memory_0_s1) & (cpu_0_data_master_granted_onchip_memory_0_s1 | ~cpu_0_data_master_qualified_request_onchip_memory_0_s1) & ((~cpu_0_data_master_qualified_request_onchip_memory_0_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_onchip_memory_0_s1 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((~cpu_0_data_master_qualified_request_seg7_lut_8_0_avalon_slave_0 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_seg7_lut_8_0_avalon_slave_0 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_timer_0_s1 | ~cpu_0_data_master_requests_timer_0_s1) & ((~cpu_0_data_master_qualified_request_timer_0_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read)));
//cascaded wait assignment, which is an e_assign
assign cpu_0_data_master_run = r_0 & r_1;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = ~cpu_0_data_master_qualified_request_timer_0_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write);
//optimize select-logic by passing only those address bits which matter.
assign cpu_0_data_master_address_to_slave = cpu_0_data_master_address[16 : 0];
//cpu_0/data_master readdata mux, which is an e_mux
assign cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_cpu_0_jtag_debug_module}} | cpu_0_jtag_debug_module_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_onchip_memory_0_s1}} | onchip_memory_0_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_timer_0_s1}} | timer_0_s1_readdata_from_sa);
//actual waitrequest port, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_waitrequest <= ~0;
else if (1)
cpu_0_data_master_waitrequest <= ~((~(cpu_0_data_master_read | cpu_0_data_master_write))? 0: (cpu_0_data_master_run & cpu_0_data_master_waitrequest));
end
//unpredictable registered wait state incoming data, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_cpu_0_data_master_readdata <= 0;
else if (1)
registered_cpu_0_data_master_readdata <= p1_registered_cpu_0_data_master_readdata;
end
//registered readdata mux, which is an e_mux
assign p1_registered_cpu_0_data_master_readdata = {32 {~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave}} | jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
//irq assign, which is an e_assign
assign cpu_0_data_master_irq = {1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
timer_0_s1_irq_from_sa,
jtag_uart_0_avalon_jtag_slave_irq_from_sa};
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
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