singt1.fit.eqn

采用vhdl语言编程

--G1_q_b[4] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[4] at M4K_X15_Y16
G1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_b[7]_PORT_B_data_in_reg = DFFE(G1_q_b[7]_PORT_B_data_in, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = GND;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_write_enable = H1L2;
G1_q_b[7]_PORT_B_write_enable_reg = DFFE(G1_q_b[7]_PORT_B_write_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = GLOBAL(clk);
G1_q_b[7]_clock_1 = !GLOBAL(A1L6);
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, G1_q_b[7]_PORT_B_data_in_reg, G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_write_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, , , , );
G1_q_b[4] = G1_q_b[7]_PORT_B_data_out[3];

--G1_q_b[5] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[5] at M4K_X15_Y16
G1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_b[7]_PORT_B_data_in_reg = DFFE(G1_q_b[7]_PORT_B_data_in, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = GND;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_write_enable = H1L2;
G1_q_b[7]_PORT_B_write_enable_reg = DFFE(G1_q_b[7]_PORT_B_write_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = GLOBAL(clk);
G1_q_b[7]_clock_1 = !GLOBAL(A1L6);
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, G1_q_b[7]_PORT_B_data_in_reg, G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_write_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, , , , );
G1_q_b[5] = G1_q_b[7]_PORT_B_data_out[2];

--G1_q_b[6] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[6] at M4K_X15_Y16
G1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_b[7]_PORT_B_data_in_reg = DFFE(G1_q_b[7]_PORT_B_data_in, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = GND;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_write_enable = H1L2;
G1_q_b[7]_PORT_B_write_enable_reg = DFFE(G1_q_b[7]_PORT_B_write_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = GLOBAL(clk);
G1_q_b[7]_clock_1 = !GLOBAL(A1L6);
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, G1_q_b[7]_PORT_B_data_in_reg, G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_write_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, , , , );
G1_q_b[6] = G1_q_b[7]_PORT_B_data_out[1];


--A1L7 is altera_internal_jtag~TDO at ELA_X0_Y15_N0
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);

--A1L8 is altera_internal_jtag~TMSUTAP at ELA_X0_Y15_N0
A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);

--A1L6 is altera_internal_jtag~TCKUTAP at ELA_X0_Y15_N0
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag at ELA_X0_Y15_N0
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);


--N1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X12_Y12_N4
--operation mode is normal

N1_state[5] = AMPP_FUNCTION(!A1L6, A1L8, N1_state[4], N1_state[3], VCC);


--K1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X12_Y10_N8
--operation mode is normal

K1_Q[2] = AMPP_FUNCTION(!A1L6, K6_Q[2], K2_Q[2], K3_Q[0], !C1L2, C1L71);


--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X12_Y11_N2
--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(!A1L6, C1_jtag_debug_mode, C1L22, C1L32, N1_state[15], N1_state[0]);


--K4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X12_Y12_N9
--operation mode is normal

K4_Q[0] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, !C1L2, C1L51);


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X8_Y10_N3
--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(!A1L6, M1_dffs[0], C1L82, M1_dffs[1], C1L72, N1_state[0], N1_state[12]);


--H1L01 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|no_name_gen~26 at LC_X13_Y10_N3
--operation mode is normal

H1L01 = AMPP_FUNCTION(K4_Q[0], C1_jtag_debug_mode_usr1, C1_jtag_debug_mode);

--K3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X13_Y10_N3
--operation mode is normal

K3_Q[0] = AMPP_FUNCTION(!A1L6, P1_dffe1a[1], !C1L2, GND, C1L1);


--H1L2 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 at LC_X13_Y10_N5
--operation mode is normal

H1L2 = AMPP_FUNCTION(H1L01, K1_Q[2], N1_state[5]);


--B1_Q1[0] is singt1:inst|Q1[0] at LC_X17_Y16_N1
--operation mode is arithmetic

B1_Q1[0]_lut_out = !B1_Q1[0];
B1_Q1[0] = DFFEAS(B1_Q1[0]_lut_out, GLOBAL(B1_CLK_CNT[4]), VCC, , , , , , );

--B1L71 is singt1:inst|Q1[0]~43 at LC_X17_Y16_N1
--operation mode is arithmetic

B1L71_cout_0 = B1_Q1[0];
B1L71 = CARRY(B1L71_cout_0);

--B1L81 is singt1:inst|Q1[0]~43COUT1_67 at LC_X17_Y16_N1
--operation mode is arithmetic

B1L81_cout_1 = B1_Q1[0];
B1L81 = CARRY(B1L81_cout_1);


--B1_Q1[1] is singt1:inst|Q1[1] at LC_X17_Y16_N2
--operation mode is arithmetic

B1_Q1[1]_lut_out = B1_Q1[1] $ (B1L71);
B1_Q1[1] = DFFEAS(B1_Q1[1]_lut_out, GLOBAL(B1_CLK_CNT[4]), VCC, , , , , , );

--B1L02 is singt1:inst|Q1[1]~47 at LC_X17_Y16_N2
--operation mode is arithmetic

B1L02_cout_0 = !B1L71 # !B1_Q1[1];
B1L02 = CARRY(B1L02_cout_0);

--B1L12 is singt1:inst|Q1[1]~47COUT1_68 at LC_X17_Y16_N2
--operation mode is arithmetic

B1L12_cout_1 = !B1L81 # !B1_Q1[1];
B1L12 = CARRY(B1L12_cout_1);


--B1_Q1[2] is singt1:inst|Q1[2] at LC_X17_Y16_N3
--operation mode is arithmetic

B1_Q1[2]_lut_out = B1_Q1[2] $ (!B1L02);
B1_Q1[2] = DFFEAS(B1_Q1[2]_lut_out, GLOBAL(B1_CLK_CNT[4]), VCC, , , , , , );

--B1L32 is singt1:inst|Q1[2]~51 at LC_X17_Y16_N3
--operation mode is arithmetic

B1L32_cout_0 = B1_Q1[2] & (!B1L02);
B1L32 = CARRY(B1L32_cout_0);

--B1L42 is singt1:inst|Q1[2]~51COUT1 at LC_X17_Y16_N3
--operation mode is arithmetic

B1L42_cout_1 = B1_Q1[2] & (!B1L12);
B1L42 = CARRY(B1L42_cout_1);


--B1_Q1[3] is singt1:inst|Q1[3] at LC_X17_Y16_N4
--operation mode is arithmetic

B1_Q1[3]_lut_out = B1_Q1[3] $ (B1L32);
B1_Q1[3] = DFFEAS(B1_Q1[3]_lut_out, GLOBAL(B1_CLK_CNT[4]), VCC, , , , , , );

--B1L62 is singt1:inst|Q1[3]~55 at LC_X17_Y16_N4
--operation mode is arithmetic

B1L62 = B1L72;


--B1_Q1[4] is singt1:inst|Q1[4] at LC_X17_Y16_N5
--operation mode is arithmetic

B1_Q1[4]_carry_eqn = (!B1L62 & GND) # (B1L62 & VCC);
B1_Q1[4]_lut_out = B1_Q1[4] $ !B1_Q1[4]_carry_eqn;
B1_Q1[4] = DFFEAS(B1_Q1[4]_lut_out, GLOBAL(B1_CLK_CNT[4]), VCC, , , , , , );

--B1L03 is singt1:inst|Q1[4]~59 at LC_X17_Y16_N5
--operation mode is arithmetic

B1L03_cout_0 = B1_Q1[4] & !B1L62;
B1L03 = CARRY(B1L03_cout_0);

--B1L13 is singt1:inst|Q1[4]~59COUT1_69 at LC_X17_Y16_N5
--operation mode is arithmetic

B1L13_cout_1 = B1_Q1[4] & !B1L62;
B1L13 = CARRY(B1L13_cout_1);


--B1_Q1[5] is singt1:inst|Q1[5] at LC_X17_Y16_N6
--operation mode is normal

B1_Q1[5]_carry_eqn = (!B1L62 & B1L03) # (B1L62 & B1L13);
B1_Q1[5]_lut_out = B1_Q1[5]_carry_eqn $ B1_Q1[5];
B1_Q1[5] = DFFEAS(B1_Q1[5]_lut_out, GLOBAL(B1_CLK_CNT[4]), VCC, , , , , , );


--H1_ram_rom_data_reg[7] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] at LC_X13_Y10_N0
--operation mode is normal

H1_ram_rom_data_reg[7] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, G1_q_b[7], H1L21, VCC, H1L24);


--H1_ram_rom_addr_reg[0] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] at LC_X14_Y10_N1
--operation mode is arithmetic

H1_ram_rom_addr_reg[0] = AMPP_FUNCTION(!A1L6, H1_ram_rom_incr_addr, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], !K1_Q[0], H1L11);

--H1L71 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~85 at LC_X14_Y10_N1
--operation mode is arithmetic

H1L71 = AMPP_FUNCTION(H1_ram_rom_incr_addr, H1_ram_rom_addr_reg[0]);

--H1L81 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~85COUT1_109 at LC_X14_Y10_N1
--operation mode is arithmetic

H1L81 = AMPP_FUNCTION(H1_ram_rom_incr_addr, H1_ram_rom_addr_reg[0]);


--H1_ram_rom_addr_reg[1] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] at LC_X14_Y10_N2
--operation mode is arithmetic

H1_ram_rom_addr_reg[1] = AMPP_FUNCTION(!A1L6, H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], !K1_Q[0], H1L11, H1L71, H1L81);

--H1L02 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~89 at LC_X14_Y10_N2
--operation mode is arithmetic

H1L02 = AMPP_FUNCTION(H1_ram_rom_addr_reg[1], H1L71);

--H1L12 is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~89COUT1_110 at LC_X14_Y10_N2
--operation mode is arithmetic

H1L12 = AMPP_FUNCTION(H1_ram_rom_addr_reg[1], H1L81);