singt1.fit.eqn

采用vhdl语言编程

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--G1_q_a[7] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[7] at M4K_X15_Y16
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
G1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_a[7]_PORT_B_data_in_reg = DFFE(G1_q_a[7]_PORT_B_data_in, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_write_enable = GND;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_write_enable = H1L2;
G1_q_a[7]_PORT_B_write_enable_reg = DFFE(G1_q_a[7]_PORT_B_write_enable, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_clock_0 = GLOBAL(clk);
G1_q_a[7]_clock_1 = !GLOBAL(A1L6);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, G1_q_a[7]_PORT_B_data_in_reg, G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, G1_q_a[7]_PORT_B_write_enable_reg, , , G1_q_a[7]_clock_0, G1_q_a[7]_clock_1, , , , );
G1_q_a[7] = G1_q_a[7]_PORT_A_data_out[0];

--G1_q_b[7] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[7] at M4K_X15_Y16
G1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_b[7]_PORT_B_data_in_reg = DFFE(G1_q_b[7]_PORT_B_data_in, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = GND;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_write_enable = H1L2;
G1_q_b[7]_PORT_B_write_enable_reg = DFFE(G1_q_b[7]_PORT_B_write_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = GLOBAL(clk);
G1_q_b[7]_clock_1 = !GLOBAL(A1L6);
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, G1_q_b[7]_PORT_B_data_in_reg, G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_write_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, , , , );
G1_q_b[7] = G1_q_b[7]_PORT_B_data_out[0];

--G1_q_a[0] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[0] at M4K_X15_Y16
G1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_a[7]_PORT_B_data_in_reg = DFFE(G1_q_a[7]_PORT_B_data_in, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_write_enable = GND;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_write_enable = H1L2;
G1_q_a[7]_PORT_B_write_enable_reg = DFFE(G1_q_a[7]_PORT_B_write_enable, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_clock_0 = GLOBAL(clk);
G1_q_a[7]_clock_1 = !GLOBAL(A1L6);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, G1_q_a[7]_PORT_B_data_in_reg, G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, G1_q_a[7]_PORT_B_write_enable_reg, , , G1_q_a[7]_clock_0, G1_q_a[7]_clock_1, , , , );
G1_q_a[0] = G1_q_a[7]_PORT_A_data_out[7];

--G1_q_a[1] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[1] at M4K_X15_Y16
G1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_a[7]_PORT_B_data_in_reg = DFFE(G1_q_a[7]_PORT_B_data_in, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_write_enable = GND;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_write_enable = H1L2;
G1_q_a[7]_PORT_B_write_enable_reg = DFFE(G1_q_a[7]_PORT_B_write_enable, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_clock_0 = GLOBAL(clk);
G1_q_a[7]_clock_1 = !GLOBAL(A1L6);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, G1_q_a[7]_PORT_B_data_in_reg, G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, G1_q_a[7]_PORT_B_write_enable_reg, , , G1_q_a[7]_clock_0, G1_q_a[7]_clock_1, , , , );
G1_q_a[1] = G1_q_a[7]_PORT_A_data_out[6];

--G1_q_a[2] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[2] at M4K_X15_Y16
G1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_a[7]_PORT_B_data_in_reg = DFFE(G1_q_a[7]_PORT_B_data_in, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_write_enable = GND;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_write_enable = H1L2;
G1_q_a[7]_PORT_B_write_enable_reg = DFFE(G1_q_a[7]_PORT_B_write_enable, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_clock_0 = GLOBAL(clk);
G1_q_a[7]_clock_1 = !GLOBAL(A1L6);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, G1_q_a[7]_PORT_B_data_in_reg, G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, G1_q_a[7]_PORT_B_write_enable_reg, , , G1_q_a[7]_clock_0, G1_q_a[7]_clock_1, , , , );
G1_q_a[2] = G1_q_a[7]_PORT_A_data_out[5];

--G1_q_a[3] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[3] at M4K_X15_Y16
G1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_a[7]_PORT_B_data_in_reg = DFFE(G1_q_a[7]_PORT_B_data_in, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_write_enable = GND;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_write_enable = H1L2;
G1_q_a[7]_PORT_B_write_enable_reg = DFFE(G1_q_a[7]_PORT_B_write_enable, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_clock_0 = GLOBAL(clk);
G1_q_a[7]_clock_1 = !GLOBAL(A1L6);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, G1_q_a[7]_PORT_B_data_in_reg, G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, G1_q_a[7]_PORT_B_write_enable_reg, , , G1_q_a[7]_clock_0, G1_q_a[7]_clock_1, , , , );
G1_q_a[3] = G1_q_a[7]_PORT_A_data_out[4];

--G1_q_a[4] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[4] at M4K_X15_Y16
G1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_a[7]_PORT_B_data_in_reg = DFFE(G1_q_a[7]_PORT_B_data_in, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_write_enable = GND;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_write_enable = H1L2;
G1_q_a[7]_PORT_B_write_enable_reg = DFFE(G1_q_a[7]_PORT_B_write_enable, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_clock_0 = GLOBAL(clk);
G1_q_a[7]_clock_1 = !GLOBAL(A1L6);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, G1_q_a[7]_PORT_B_data_in_reg, G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, G1_q_a[7]_PORT_B_write_enable_reg, , , G1_q_a[7]_clock_0, G1_q_a[7]_clock_1, , , , );
G1_q_a[4] = G1_q_a[7]_PORT_A_data_out[3];

--G1_q_a[5] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[5] at M4K_X15_Y16
G1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_a[7]_PORT_B_data_in_reg = DFFE(G1_q_a[7]_PORT_B_data_in, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_write_enable = GND;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_write_enable = H1L2;
G1_q_a[7]_PORT_B_write_enable_reg = DFFE(G1_q_a[7]_PORT_B_write_enable, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_clock_0 = GLOBAL(clk);
G1_q_a[7]_clock_1 = !GLOBAL(A1L6);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, G1_q_a[7]_PORT_B_data_in_reg, G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, G1_q_a[7]_PORT_B_write_enable_reg, , , G1_q_a[7]_clock_0, G1_q_a[7]_clock_1, , , , );
G1_q_a[5] = G1_q_a[7]_PORT_A_data_out[2];

--G1_q_a[6] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_a[6] at M4K_X15_Y16
G1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_a[7]_PORT_B_data_in_reg = DFFE(G1_q_a[7]_PORT_B_data_in, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_PORT_A_write_enable = GND;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_write_enable = H1L2;
G1_q_a[7]_PORT_B_write_enable_reg = DFFE(G1_q_a[7]_PORT_B_write_enable, G1_q_a[7]_clock_1, , , );
G1_q_a[7]_clock_0 = GLOBAL(clk);
G1_q_a[7]_clock_1 = !GLOBAL(A1L6);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, G1_q_a[7]_PORT_B_data_in_reg, G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, G1_q_a[7]_PORT_B_write_enable_reg, , , G1_q_a[7]_clock_0, G1_q_a[7]_clock_1, , , , );
G1_q_a[6] = G1_q_a[7]_PORT_A_data_out[1];

--G1_q_b[0] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[0] at M4K_X15_Y16
G1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_b[7]_PORT_B_data_in_reg = DFFE(G1_q_b[7]_PORT_B_data_in, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = GND;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_write_enable = H1L2;
G1_q_b[7]_PORT_B_write_enable_reg = DFFE(G1_q_b[7]_PORT_B_write_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = GLOBAL(clk);
G1_q_b[7]_clock_1 = !GLOBAL(A1L6);
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, G1_q_b[7]_PORT_B_data_in_reg, G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_write_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, , , , );
G1_q_b[0] = G1_q_b[7]_PORT_B_data_out[7];

--G1_q_b[1] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[1] at M4K_X15_Y16
G1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_b[7]_PORT_B_data_in_reg = DFFE(G1_q_b[7]_PORT_B_data_in, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = GND;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_write_enable = H1L2;
G1_q_b[7]_PORT_B_write_enable_reg = DFFE(G1_q_b[7]_PORT_B_write_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = GLOBAL(clk);
G1_q_b[7]_clock_1 = !GLOBAL(A1L6);
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, G1_q_b[7]_PORT_B_data_in_reg, G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_write_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, , , , );
G1_q_b[1] = G1_q_b[7]_PORT_B_data_out[6];

--G1_q_b[2] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[2] at M4K_X15_Y16
G1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_b[7]_PORT_B_data_in_reg = DFFE(G1_q_b[7]_PORT_B_data_in, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = GND;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_write_enable = H1L2;
G1_q_b[7]_PORT_B_write_enable_reg = DFFE(G1_q_b[7]_PORT_B_write_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = GLOBAL(clk);
G1_q_b[7]_clock_1 = !GLOBAL(A1L6);
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, G1_q_b[7]_PORT_B_data_in_reg, G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_write_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, , , , );
G1_q_b[2] = G1_q_b[7]_PORT_B_data_out[5];

--G1_q_b[3] is singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_5ls:auto_generated|altsyncram_aaa2:altsyncram1|q_b[3] at M4K_X15_Y16
G1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
G1_q_b[7]_PORT_A_data_in_reg = DFFE(G1_q_b[7]_PORT_A_data_in, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[7], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[0]);
G1_q_b[7]_PORT_B_data_in_reg = DFFE(G1_q_b[7]_PORT_B_data_in, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_address = BUS(B1_Q1[0], B1_Q1[1], B1_Q1[2], B1_Q1[3], B1_Q1[4], B1_Q1[5]);
G1_q_b[7]_PORT_A_address_reg = DFFE(G1_q_b[7]_PORT_A_address, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_address = BUS(H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4], H1_ram_rom_addr_reg[5]);
G1_q_b[7]_PORT_B_address_reg = DFFE(G1_q_b[7]_PORT_B_address, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_PORT_A_write_enable = GND;
G1_q_b[7]_PORT_A_write_enable_reg = DFFE(G1_q_b[7]_PORT_A_write_enable, G1_q_b[7]_clock_0, , , );
G1_q_b[7]_PORT_B_write_enable = H1L2;
G1_q_b[7]_PORT_B_write_enable_reg = DFFE(G1_q_b[7]_PORT_B_write_enable, G1_q_b[7]_clock_1, , , );
G1_q_b[7]_clock_0 = GLOBAL(clk);
G1_q_b[7]_clock_1 = !GLOBAL(A1L6);
G1_q_b[7]_PORT_B_data_out = MEMORY(G1_q_b[7]_PORT_A_data_in_reg, G1_q_b[7]_PORT_B_data_in_reg, G1_q_b[7]_PORT_A_address_reg, G1_q_b[7]_PORT_B_address_reg, G1_q_b[7]_PORT_A_write_enable_reg, G1_q_b[7]_PORT_B_write_enable_reg, , , G1_q_b[7]_clock_0, G1_q_b[7]_clock_1, , , , );
G1_q_b[3] = G1_q_b[7]_PORT_B_data_out[4];