singt1.jdi

采用vhdl语言编程

<sld_project_info>
  <hub_info ir_width="8" node_count="2"/>
  <node_info>
    <node hpath="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|sld_mod_ram_rom:mgl_prim2" instance_id="0" mfg_id="110" node_id="3" sld_node_info="0x8186E00" version="1">
      <parameters>
        <parameter name="sld_node_info" type="dec" value="135818752"/>
        <parameter name="sld_auto_instance_index" type="string" value="yes"/>
        <parameter name="sld_ip_version" type="dec" value="1"/>
        <parameter name="sld_ip_minor_version" type="dec" value="3"/>
        <parameter name="sld_common_ip_version" type="dec" value="0"/>
        <parameter name="width_word" type="unknown" value="8"/>
        <parameter name="numwords" type="unknown" value="64"/>
        <parameter name="widthad" type="unknown" value="6"/>
        <parameter name="shift_count_bits" type="unknown" value="4"/>
        <parameter name="cvalue" type="unknown" value="00000000"/>
        <parameter name="is_data_in_ram" type="unknown" value="1"/>
        <parameter name="is_readable" type="unknown" value="1"/>
        <parameter name="node_name" type="unknown" value="0"/>
        <parameter name=" constraint(address)" type="string" value="5 downto 0"/>
      </parameters>
      <inputs>
        <port name="data_read[0]" source="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_b[0]"/>
        <port name="data_read[1]" source="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_b[1]"/>
        <port name="data_read[2]" source="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_b[2]"/>
        <port name="data_read[3]" source="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_b[3]"/>
        <port name="data_read[4]" source="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_b[4]"/>
        <port name="data_read[5]" source="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_b[5]"/>
        <port name="data_read[6]" source="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_b[6]"/>
        <port name="data_read[7]" source="singt1:inst|data_rom:u1|altsyncram:altsyncram_component|altsyncram_fo51:auto_generated|altsyncram_m372:altsyncram1|q_b[7]"/>
        <port name="raw_tck" source="altera_internal_jtag"/>
        <port name="tdi" source="altera_internal_jtag"/>
        <port name="usr1" source="sld_hub:sld_hub_inst|jtag_debug_mode_usr1"/>
        <port name="jtag_state_cdr" source="sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]"/>
        <port name="jtag_state_sdr" source="sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]"/>
        <port name="jtag_state_e1dr" source="sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]"/>
        <port name="jtag_state_udr" source="sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]"/>
        <port name="jtag_state_uir" source="sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15]"/>
        <port name="clrn" source="sld_hub:sld_hub_inst|CLR_SIGNAL"/>
        <port name="ena" source="sld_hub:sld_hub_inst|node_ena~1"/>
        <port name="ir_in[0]" source="sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]"/>
        <port name="ir_in[1]" source="sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]"/>
        <port name="ir_in[2]" source="sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]"/>
        <port name="ir_in[3]" source="sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]"/>
        <port name="ir_in[4]" source="sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]"/>
      </inputs>
      <outputs>
        <port name="tck_usr"/>
        <port name="address[0]"/>
        <port name="address[1]"/>
        <port name="address[2]"/>
        <port name="address[3]"/>
        <port name="address[4]"/>
        <port name="address[5]"/>
        <port name="enable_write"/>
        <port name="data_write[0]"/>
        <port name="data_write[1]"/>
        <port name="data_write[2]"/>
        <port name="data_write[3]"/>
        <port name="data_write[4]"/>
        <port name="data_write[5]"/>
        <port name="data_write[6]"/>
        <port name="data_write[7]"/>
        <port name="ir_out[0]"/>
        <port name="ir_out[1]"/>
        <port name="ir_out[2]"/>
        <port name="ir_out[3]"/>
        <port name="ir_out[4]"/>
        <port name="irq"/>
        <port name="tdo"/>
      </outputs>
    </node>
    <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x28006E00" version="5">
      <parameters>
        <parameter name="lpm_type" type="string" value="sld_signaltap"/>
        <parameter name="sld_node_info" type="unknown" value="671116800"/>
        <parameter name="sld_ip_version" type="dec" value="5"/>
        <parameter name="sld_ip_minor_version" type="dec" value="0"/>
        <parameter name="sld_common_ip_version" type="dec" value="0"/>
        <parameter name="sld_data_bits" type="unknown" value="8"/>
        <parameter name="sld_trigger_bits" type="unknown" value="8"/>
        <parameter name="sld_data_bit_cntr_bits" type="unknown" value="3"/>
        <parameter name="sld_node_crc_bits" type="dec" value="32"/>
        <parameter name="sld_node_crc_hiword" type="unknown" value="23726"/>
        <parameter name="sld_node_crc_loword" type="unknown" value="36856"/>
        <parameter name="sld_incremental_routing" type="dec" value="0"/>
        <parameter name="sld_sample_depth" type="unknown" value="8192"/>
        <parameter name="sld_mem_address_bits" type="unknown" value="13"/>
        <parameter name="sld_ram_block_type" type="string" value="AUTO"/>
        <parameter name="sld_trigger_level" type="unknown" value="1"/>
        <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
        <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
        <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
        <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
        <parameter name="sld_advanced_trigger_1" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_2" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_3" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_4" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_5" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_6" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_7" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_8" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_9" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_10" type="string" value="NONE"/>
        <parameter name="sld_inversion_mask_length" type="unknown" value="46"/>
        <parameter name="sld_inversion_mask" type="unknown" value="0000000000000000000000000000000000000000000000"/>
        <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
      </parameters>
      <inputs>
        <port name="acq_clk" source="clk"/>
        <port name="acq_trigger_in[0]" source="dout[0]"/>
        <port name="acq_data_in[0]" source="dout[0]"/>
        <port name="acq_trigger_in[1]" source="dout[1]"/>
        <port name="acq_data_in[1]" source="dout[1]"/>
        <port name="acq_trigger_in[2]" source="dout[2]"/>
        <port name="acq_data_in[2]" source="dout[2]"/>
        <port name="acq_trigger_in[3]" source="dout[3]"/>
        <port name="acq_data_in[3]" source="dout[3]"/>
        <port name="acq_trigger_in[4]" source="dout[4]"/>
        <port name="acq_data_in[4]" source="dout[4]"/>
        <port name="acq_trigger_in[5]" source="dout[5]"/>
        <port name="acq_data_in[5]" source="dout[5]"/>
        <port name="acq_trigger_in[6]" source="dout[6]"/>
        <port name="acq_data_in[6]" source="dout[6]"/>
        <port name="acq_trigger_in[7]" source="dout[7]"/>
        <port name="acq_data_in[7]" source="dout[7]"/>
      </inputs>
      <outputs/>
    </node>
  </node_info>
</sld_project_info>