display.v

来自「数字钟设计」· Verilog 代码 · 共 39 行

module display(
               Display,     //outputs

               counter_display, //inputs
               timer_display,
               setup_enable,
               sel);
output   [6:0]Display;
input    [6:0]counter_display;
input    [6:0]timer_display;
input         setup_enable;
input         sel;
wire      [6:0]Disp_Temp;
reg       [6:0]Display;
assign   Disp_Temp=(setup_enable&&sel)?timer_display:counter_display;
always@(Disp_Temp)
 begin
  case(Disp_Temp)
   4'b0000:Display=7'b1000000;
   4'b0001:Display=7'b1001111;
   4'b0010:Display=7'b0100100;
   4'b0011:Display=7'b0110000;
   4'b0100:Display=7'b0011001;
   4'b0101:Display=7'b0010010;
   4'b0110:Display=7'b0000010;
   4'b0111:Display=7'b1011000;
   4'b1000:Display=7'b0000000;
   4'b1001:Display=7'b0010000;
   default:Display=7'b1111111;
  endcase
 end

endmodule