bin2led1.txt

来自「用VHDL编译的源代码」· 文本 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
entity bin2led1 is
   port(
      bin1: in std_logic_vector(3 downto 0);
      sseg1: out std_logic_vector(6 downto 0)
   );
end bin2led1;

architecture arch of bin2led1 is
begin
   with bin1 select
      sseg1 <=
         "1001111" when "0000",
         "1111001" when "0001",
         "1111111" when "0010",
         "1111111" when others; 
end arch;