f_adder.map.rpt

全加器

+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                               ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                  ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------+
; f_adder.vhd                      ; yes             ; User VHDL File  ; D:/Quatus2/works/summrize/f_adder/f_adder.vhd ;
; h_adder.vhd                      ; yes             ; User VHDL File  ; D:/Quatus2/works/summrize/f_adder/h_adder.vhd ;
; or2a.vhd                         ; yes             ; User VHDL File  ; D:/Quatus2/works/summrize/f_adder/or2a.vhd    ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 2     ;
;     -- Combinational with no register       ; 2     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 2     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 2     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 5     ;
; Maximum fan-out node                        ; bin   ;
; Maximum fan-out                             ; 2     ;
; Total fan-out                               ; 8     ;
; Average fan-out                             ; 1.14  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |f_adder                   ; 2 (0)       ; 0            ; 0           ; 5    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |f_adder            ;
;    |h_adder:u2|            ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |f_adder|h_adder:u2 ;
;    |or2a:u3|               ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |f_adder|or2a:u3    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Quatus2/works/summrize/f_adder/f_adder.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Nov 02 19:25:47 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off f_adder -c f_adder
Info: Found 2 design units, including 1 entities, in source file f_adder.vhd
    Info: Found design unit 1: f_adder-fd1
    Info: Found entity 1: f_adder
Info: Found 2 design units, including 1 entities, in source file h_adder.vhd
    Info: Found design unit 1: h_adder-fh1
    Info: Found entity 1: h_adder
Info: Found 2 design units, including 1 entities, in source file or2a.vhd
    Info: Found design unit 1: or2a-a
    Info: Found entity 1: or2a
Info: Elaborating entity "f_adder" for the top level hierarchy
Info: Elaborating entity "h_adder" for hierarchy "h_adder:u1"
Info: Elaborating entity "or2a" for hierarchy "or2a:u3"
Info: Implemented 7 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 2 output pins
    Info: Implemented 2 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Nov 02 19:25:50 2008
    Info: Elapsed time: 00:00:03