xulie5.tan.qmsg

来自「本设计是一个序列检测器」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "xulie5.bdf" "" { Schematic "D:/Quartus/xulie5/xulie5.bdf" { { 528 296 464 544 "CLK" "" } } } } { "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register 74161:inst\|f74161:sub\|9 74161:inst\|f74161:sub\|110 200.0 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 200.0 MHz between source register \"74161:inst\|f74161:sub\|9\" and destination register \"74161:inst\|f74161:sub\|110\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.200 ns + Longest register register " "Info: + Longest register to register delay is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74161:inst\|f74161:sub\|9 1 REG LC2_L2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_L2; Fanout = 3; REG Node = '74161:inst\|f74161:sub\|9'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74161:inst|f74161:sub|9 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 128 640 704 208 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.700 ns) 0.900 ns 74161:inst\|f74161:sub\|81 2 COMB LC2_L2 2 " "Info: 2: + IC(0.200 ns) + CELL(0.700 ns) = 0.900 ns; Loc. = LC2_L2; Fanout = 2; COMB Node = '74161:inst\|f74161:sub\|81'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { 74161:inst|f74161:sub|9 74161:inst|f74161:sub|81 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 256 432 480 288 "81" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.100 ns 74161:inst\|f74161:sub\|85 3 COMB LC3_L2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 1.100 ns; Loc. = LC3_L2; Fanout = 2; COMB Node = '74161:inst\|f74161:sub\|85'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { 74161:inst|f74161:sub|81 74161:inst|f74161:sub|85 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 464 432 480 496 "85" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 1.300 ns 74161:inst\|f74161:sub\|95 4 COMB LC4_L2 1 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 1.300 ns; Loc. = LC4_L2; Fanout = 1; COMB Node = '74161:inst\|f74161:sub\|95'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { 74161:inst|f74161:sub|85 74161:inst|f74161:sub|95 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 672 432 480 704 "95" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 2.200 ns 74161:inst\|f74161:sub\|110 5 REG LC5_L2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.900 ns) = 2.200 ns; Loc. = LC5_L2; Fanout = 2; REG Node = '74161:inst\|f74161:sub\|110'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { 74161:inst|f74161:sub|95 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 90.91 % ) " "Info: Total cell delay = 2.000 ns ( 90.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 9.09 % ) " "Info: Total interconnect delay = 0.200 ns ( 9.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { 74161:inst|f74161:sub|9 74161:inst|f74161:sub|81 74161:inst|f74161:sub|85 74161:inst|f74161:sub|95 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { 74161:inst|f74161:sub|9 74161:inst|f74161:sub|81 74161:inst|f74161:sub|85 74161:inst|f74161:sub|95 74161:inst|f74161:sub|110 } { 0.000ns 0.200ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.700ns 0.200ns 0.200ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "xulie5.bdf" "" { Schematic "D:/Quartus/xulie5/xulie5.bdf" { { 528 296 464 544 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns 74161:inst\|f74161:sub\|110 2 REG LC5_L2 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_L2; Fanout = 2; REG Node = '74161:inst\|f74161:sub\|110'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out 74161:inst|f74161:sub|110 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "xulie5.bdf" "" { Schematic "D:/Quartus/xulie5/xulie5.bdf" { { 528 296 464 544 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns 74161:inst\|f74161:sub\|9 2 REG LC2_L2 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_L2; Fanout = 3; REG Node = '74161:inst\|f74161:sub\|9'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK 74161:inst|f74161:sub|9 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 128 640 704 208 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK 74161:inst|f74161:sub|9 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out 74161:inst|f74161:sub|9 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out 74161:inst|f74161:sub|110 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK 74161:inst|f74161:sub|9 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out 74161:inst|f74161:sub|9 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 128 640 704 208 "9" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { 74161:inst|f74161:sub|9 74161:inst|f74161:sub|81 74161:inst|f74161:sub|85 74161:inst|f74161:sub|95 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { 74161:inst|f74161:sub|9 74161:inst|f74161:sub|81 74161:inst|f74161:sub|85 74161:inst|f74161:sub|95 74161:inst|f74161:sub|110 } { 0.000ns 0.200ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.700ns 0.200ns 0.200ns 0.900ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out 74161:inst|f74161:sub|110 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK 74161:inst|f74161:sub|9 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out 74161:inst|f74161:sub|9 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { 74161:inst|f74161:sub|110 } {  } {  } "" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK co 74161:inst\|f74161:sub\|110 15.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"co\" through register \"74161:inst\|f74161:sub\|110\" is 15.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "xulie5.bdf" "" { Schematic "D:/Quartus/xulie5/xulie5.bdf" { { 528 296 464 544 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns 74161:inst\|f74161:sub\|110 2 REG LC5_L2 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_L2; Fanout = 2; REG Node = '74161:inst\|f74161:sub\|110'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out 74161:inst|f74161:sub|110 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.000 ns + Longest register pin " "Info: + Longest register to pin delay is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74161:inst\|f74161:sub\|110 1 REG LC5_L2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_L2; Fanout = 2; REG Node = '74161:inst\|f74161:sub\|110'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "f74161.bdf" "" { Schematic "d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 2.400 ns inst16~118 2 COMB LC6_L2 1 " "Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC6_L2; Fanout = 1; COMB Node = 'inst16~118'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { 74161:inst|f74161:sub|110 inst16~118 } "NODE_NAME" } } { "xulie5.bdf" "" { Schematic "D:/Quartus/xulie5/xulie5.bdf" { { 200 752 856 312 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(8.500 ns) 12.000 ns co 3 PIN PIN_104 0 " "Info: 3: + IC(1.100 ns) + CELL(8.500 ns) = 12.000 ns; Loc. = PIN_104; Fanout = 0; PIN Node = 'co'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "9.600 ns" { inst16~118 co } "NODE_NAME" } } { "xulie5.bdf" "" { Schematic "D:/Quartus/xulie5/xulie5.bdf" { { 264 1120 1296 280 "co" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.700 ns ( 89.17 % ) " "Info: Total cell delay = 10.700 ns ( 89.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 10.83 % ) " "Info: Total interconnect delay = 1.300 ns ( 10.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { 74161:inst|f74161:sub|110 inst16~118 co } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { 74161:inst|f74161:sub|110 inst16~118 co } { 0.000ns 0.200ns 1.100ns } { 0.000ns 2.200ns 8.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK 74161:inst|f74161:sub|110 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out 74161:inst|f74161:sub|110 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { 74161:inst|f74161:sub|110 inst16~118 co } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { 74161:inst|f74161:sub|110 inst16~118 co } { 0.000ns 0.200ns 1.100ns } { 0.000ns 2.200ns 8.500ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 14 08:13:36 2007 " "Info: Processing ended: Wed Nov 14 08:13:36 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}